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test ports containers
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nulinspiratie committed Jul 3, 2024
1 parent 742385b commit 514e4e0
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Showing 2 changed files with 76 additions and 6 deletions.
11 changes: 5 additions & 6 deletions quam/components/ports/ports_containers.py
Original file line number Diff line number Diff line change
Expand Up @@ -83,18 +83,16 @@ def _get_port(

return ports[port_id]

def get_port_from_reference(
self, port_reference: str, create=False
) -> OPXPlusPortTypes:
def reference_to_port(self, port_reference: str, create=False) -> OPXPlusPortTypes:
elems = port_reference.split("/")
port_type, controller_id, port_id = elems[-3:]

port_type = port_type[:-1]
if controller_id.isdigit():
controller_id = int(controller_id)
fem_id = int(fem_id)
port_id = int(port_id)

return self._get_port(controller_id, fem_id, port_id, port_type, create=create)
return self._get_port(controller_id, port_id, port_type, create=create)

def get_analog_output(
self,
Expand Down Expand Up @@ -217,7 +215,7 @@ def _get_port(

return ports[port_id]

def get_port_from_reference(
def reference_to_port(
self,
port_reference: Union[QuamComponent, str],
attr: Optional[str] = None,
Expand All @@ -232,6 +230,7 @@ def get_port_from_reference(
elems = port_reference.split("/")
port_type, controller_id, fem_id, port_id = elems[-4:]

port_type = port_type[:-1]
if controller_id.isdigit():
controller_id = int(controller_id)
fem_id = int(fem_id)
Expand Down
71 changes: 71 additions & 0 deletions tests/components/ports/test_ports_containers.py
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,40 @@ def test_opx_plus_ports_container_add_ports(port_type):
assert port is ports_group["con2"][3]


@pytest.mark.parametrize(
"port_type", ["analog_output", "analog_input", "digital_output", "digital_input"]
)
def test_opx_plus_ports_container_reference_to_port(port_type):
port_mapping = {
"analog_output": OPXPlusAnalogOutputPort,
"analog_input": OPXPlusAnalogInputPort,
"digital_output": OPXPlusDigitalOutputPort,
"digital_input": OPXPlusDigitalInputPort,
}

ports_container = OPXPlusPortsContainer()

port_reference = f"#/{port_type}s/con1/3"

with pytest.raises(KeyError):
ports_container.reference_to_port(port_reference)

port = ports_container.reference_to_port(port_reference, create=True)
assert isinstance(port, port_mapping[port_type])

assert port.controller_id == "con1"
assert port.port_id == 3

port2 = ports_container.reference_to_port(port_reference, create=False)
assert port is port2

port3 = ports_container.reference_to_port(port_reference, create=True)
assert port is port3

ports_group = getattr(ports_container, f"{port_type}s")
assert port is ports_group["con1"][3]


@pytest.mark.parametrize(
"port_type",
["analog_output", "analog_input", "mw_output", "mw_input", "digital_output"],
Expand Down Expand Up @@ -104,3 +138,40 @@ def test_fem_ports_container_add_ports(port_type):

ports_group = getattr(ports_container, f"{port_type}s")
assert port is ports_group["con2"][2][3]


@pytest.mark.parametrize(
"port_type",
["analog_output", "analog_input", "mw_output", "mw_input", "digital_output"],
)
def test_fem_ports_container_reference_to_port(port_type):
port_mapping = {
"analog_output": LFFEMAnalogOutputPort,
"analog_input": LFFEMAnalogInputPort,
"mw_output": MWFEMAnalogOutputPort,
"mw_input": MWFEMAnalogInputPort,
"digital_output": FEMDigitalOutputPort,
}

port_reference = f"#/{port_type}s/con1/2/3"

ports_container = FEMPortsContainer()

with pytest.raises(KeyError):
ports_container.reference_to_port(port_reference)

port = ports_container.reference_to_port(port_reference, create=True)
assert isinstance(port, port_mapping[port_type])

assert port.controller_id == "con1"
assert port.fem_id == 2
assert port.port_id == 3

port2 = ports_container.reference_to_port(port_reference, create=False)
assert port is port2

port3 = ports_container.reference_to_port(port_reference, create=True)
assert port is port3

ports_group = getattr(ports_container, f"{port_type}s")
assert port is ports_group["con1"][2][3]

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