added tests for ports

quam/components/ports.py

@@ -94,7 +94,9 @@ def get_port_config(
                 )
 
         controller_cfg = config["controllers"].setdefault(controller_name, {})
-        ports_cfg = controller_cfg.setdefault(f"{self.port_type}s", {})
+        fems_cfg = controller_cfg.setdefault("fems", {})
+        fem_cfg = fems_cfg.setdefault(fem, {})
+        ports_cfg = fem_cfg.setdefault(f"{self.port_type}s", {})
         port_cfg = ports_cfg.setdefault(port, {})
         return port_cfg
 
@@ -185,15 +187,18 @@ class MWFEMAnalogOutputPort(FEMPort):
     full_scale_power_dbm: int = -11
 
     def get_port_properties(self) -> Dict[str, Any]:
-        return {
+        port_cfg = {
             "band": self.band,
-            "upconverter_frequency": self.upconverter_frequency,
-            "upconverters": self.upconverters,
             "delay": self.delay,
             "shareable": self.shareable,
             "sampling_rate": self.sampling_rate,
             "full_scale_power_dbm": self.full_scale_power_dbm,
         }
+        if self.upconverter_frequency is not None:
+            port_cfg["upconverter_frequency"] = self.upconverter_frequency
+        if self.upconverters is not None:
+            port_cfg["upconverters"] = self.upconverters
+        return port_cfg
 
 
 @quam_dataclass
@@ -233,8 +238,10 @@ class OPXPlusDigitalOutputPort(DigitalOutputPort, OPXPlusPort):
 
 @quam_dataclass
 class OPXPlusDigitalInputPort(OPXPlusPort):
+    port_type: ClassVar[str] = "digital_input"
+
     deadtime: int = 4
-    polarity: Literal["Rising", "Falling"] = "Rising"
+    polarity: Literal["rising", "falling"] = "rising"
     threshold: float = 2.0
     shareable: bool = False
 

tests/components/ports/test_digital_ports.py

@@ -0,0 +1,117 @@
+import pytest
+
+from quam.components.ports import (
+    FEMDigitalOutputPort,
+    OPXPlusDigitalInputPort,
+    OPXPlusDigitalOutputPort,
+)
+
+
+def test_opx_plus_digital_output_port():
+    with pytest.raises(TypeError):
+        OPXPlusDigitalOutputPort()
+
+    port = OPXPlusDigitalOutputPort(port=("con1", 2))
+    assert port.port == ("con1", 2)
+    assert port.port_type == "digital_output"
+    assert port.inverted == False
+    assert port.shareable == False
+
+    assert port.get_port_properties() == {
+        "inverted": False,
+        "shareable": False,
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "digital_outputs": {
+                    2: {
+                        "inverted": False,
+                        "shareable": False,
+                    }
+                }
+            }
+        }
+    }
+
+
+def test_opx_plus_digital_input_port():
+    with pytest.raises(TypeError):
+        OPXPlusDigitalInputPort()
+
+    port = OPXPlusDigitalInputPort(port=("con1", 2))
+    assert port.port == ("con1", 2)
+    assert port.port_type == "digital_input"
+    assert port.deadtime == 4
+    assert port.polarity == "rising"
+    assert port.threshold == 2.0
+    assert port.shareable == False
+
+    assert port.get_port_properties() == {
+        "deadtime": 4,
+        "polarity": "rising",
+        "threshold": 2.0,
+        "shareable": False,
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "digital_inputs": {
+                    2: {
+                        "deadtime": 4,
+                        "polarity": "rising",
+                        "threshold": 2.0,
+                        "shareable": False,
+                    }
+                }
+            }
+        }
+    }
+
+
+def test_fem_digital_output_port():
+    with pytest.raises(TypeError):
+        FEMDigitalOutputPort()
+
+    port = FEMDigitalOutputPort(port=("con1", 1, 2))
+
+    assert port.port == ("con1", 1, 2)
+    assert port.port_type == "digital_output"
+    assert port.inverted == False
+    assert port.shareable == False
+    assert port.level == "LVTTL"
+
+    assert port.get_port_properties() == {
+        "inverted": False,
+        "shareable": False,
+        "level": "LVTTL",
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "fems": {
+                    1: {
+                        "digital_outputs": {
+                            2: {
+                                "inverted": False,
+                                "shareable": False,
+                                "level": "LVTTL",
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }

tests/components/ports/test_lf_fem_analog_ports.py

@@ -0,0 +1,102 @@
+import pytest
+
+from quam.components.ports import LFFEMAnalogInputPort, LFFEMAnalogOutputPort
+
+
+def test_lf_fem_analog_output_port():
+    with pytest.raises(TypeError):
+        LFFEMAnalogOutputPort()
+
+    port = LFFEMAnalogOutputPort(port=("con1", 1, 2))
+    assert port.port == ("con1", 1, 2)
+    assert port.port_type == "analog_output"
+    assert port.offset == 0.0
+    assert port.delay == 0
+    assert port.crosstalk == {}
+    assert port.feedforward_filter == []
+    assert port.feedback_filter == []
+    assert port.shareable == False
+    assert port.output_mode == "direct"
+    assert port.sampling_rate == 1e9
+    assert port.upsampling_mode == "mw"
+
+    assert port.get_port_properties() == {
+        "offset": 0.0,
+        "delay": 0,
+        "crosstalk": {},
+        "feedforward_filter": [],
+        "feedback_filter": [],
+        "shareable": False,
+        "output_mode": "direct",
+        "sampling_rate": 1e9,
+        "upsampling_mode": "mw",
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "fems": {
+                    1: {
+                        "analog_outputs": {
+                            2: {
+                                "offset": 0.0,
+                                "delay": 0,
+                                "crosstalk": {},
+                                "feedforward_filter": [],
+                                "feedback_filter": [],
+                                "shareable": False,
+                                "output_mode": "direct",
+                                "sampling_rate": 1e9,
+                                "upsampling_mode": "mw",
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+
+def test_lf_fem_analog_input_port():
+    with pytest.raises(TypeError):
+        LFFEMAnalogInputPort()
+
+    port = LFFEMAnalogInputPort(port=("con1", 1, 2))
+    assert port.port == ("con1", 1, 2)
+    assert port.port_type == "analog_input"
+    assert port.offset == 0.0
+    assert port.gain_db == 0
+    assert port.shareable == False
+    assert port.sampling_rate == 1e9
+
+    assert port.get_port_properties() == {
+        "offset": 0.0,
+        "gain_db": 0,
+        "shareable": False,
+        "sampling_rate": 1e9,
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "fems": {
+                    1: {
+                        "analog_inputs": {
+                            2: {
+                                "offset": 0.0,
+                                "gain_db": 0,
+                                "shareable": False,
+                                "sampling_rate": 1e9,
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }

tests/components/ports/test_mw_fem_analog_ports.py

@@ -0,0 +1,112 @@
+import pytest
+
+from quam.components.ports import MWFEMAnalogInputPort, MWFEMAnalogOutputPort
+
+
+def test_mw_fem_analog_output_port():
+    with pytest.raises(TypeError):
+        MWFEMAnalogOutputPort()
+
+    with pytest.raises(TypeError):
+        port = MWFEMAnalogOutputPort(port=("con1", 1, 2))
+
+    port = MWFEMAnalogOutputPort(port=("con1", 1, 2), band=1)
+    assert port.port == ("con1", 1, 2)
+    assert port.port_type == "analog_output"
+    assert port.band == 1
+    assert port.upconverter_frequency is None
+    assert port.upconverters is None
+    assert port.delay == 0
+    assert port.shareable == False
+    assert port.sampling_rate == 1e9
+    assert port.full_scale_power_dbm == -11
+
+    assert port.get_port_properties() == {
+        "band": 1,
+        "delay": 0,
+        "shareable": False,
+        "sampling_rate": 1e9,
+        "full_scale_power_dbm": -11,
+    }
+
+    port.upconverter_frequency = 5e9
+    assert port.get_port_properties() == {
+        "band": 1,
+        "upconverter_frequency": 5e9,
+        "delay": 0,
+        "shareable": False,
+        "sampling_rate": 1e9,
+        "full_scale_power_dbm": -11,
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "fems": {
+                    1: {
+                        "analog_outputs": {
+                            2: {
+                                "band": 1,
+                                "upconverter_frequency": 5e9,
+                                "delay": 0,
+                                "shareable": False,
+                                "sampling_rate": 1e9,
+                                "full_scale_power_dbm": -11,
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+
+def test_mw_fem_analog_input_ports():
+    with pytest.raises(TypeError):
+        MWFEMAnalogInputPort()
+
+    with pytest.raises(TypeError):
+        port = MWFEMAnalogInputPort(port=("con1", 1, 2))
+
+    port = MWFEMAnalogInputPort(
+        port=("con1", 1, 2), band=1, downconverter_frequency=5e9
+    )
+
+    assert port.port == ("con1", 1, 2)
+    assert port.port_type == "analog_input"
+    assert port.band == 1
+    assert port.downconverter_frequency == 5e9
+    assert port.sampling_rate == 1e9
+    assert port.shareable == False
+
+    assert port.get_port_properties() == {
+        "band": 1,
+        "downconverter_frequency": 5e9,
+        "sampling_rate": 1e9,
+        "shareable": False,
+    }
+
+    cfg = {"controllers": {}}
+    port.apply_to_config(cfg)
+
+    assert cfg == {
+        "controllers": {
+            "con1": {
+                "fems": {
+                    1: {
+                        "analog_inputs": {
+                            2: {
+                                "band": 1,
+                                "downconverter_frequency": 5e9,
+                                "sampling_rate": 1e9,
+                                "shareable": False,
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }