sphinx typos

src/qililab/digital/circuit_transpiler.py

@@ -61,6 +61,7 @@ def transpile_circuits(
         And finally, it converts the native gate circuit to a pulse schedule using calibrated settings from the runcard.
 
         If ``optimize=True`` (default behaviour), then it also does some circuit optimization:
+
         - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
         - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
 

src/qililab/execute_circuit.py

@@ -40,11 +40,13 @@ def execute(
 
     The transpilation is done with the :class:`CircuitTranspiler`, ``transpile_circuits()`` method, refer to it for more detailed information,
     but the main stages of this process are:
+
     - Making the routing and placement of the circuit into the chip physical connectivity.
     - Translates the gates into the system native's gates (CZ, RZ, Drag, Wait and M (Measurement).
     - Converts the native gates to a pulse schedule using calibrated settings from the runcard.
 
     If ``optimize=True`` (default behaviour), then the transpilation also does some circuit optimization:
+
     - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
     - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
 

src/qililab/platform/platform.py

@@ -916,11 +916,13 @@ def execute(
 
         The transpilation is done with the :class:`CircuitTranspiler`, ``transpile_circuits()`` method, refer to it for more detailed information,
         but the main stages of this process are:
+
         - Making the routing and placement of the circuit into the chip physical connectivity.
         - Translates the gates into the system native's gates (CZ, RZ, Drag, Wait and M (Measurement).
         - Converts the native gates to a pulse schedule using calibrated settings from the runcard.
 
         If ``optimize=True`` (default behaviour), then the transpilation also does some circuit optimization:
+
         - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
         - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
 
@@ -1053,11 +1055,13 @@ def compile(
 
         The transpilation is done with the :class:`CircuitTranspiler`, ``transpile_circuits()`` method, refer to it for more detailed information,
         but the main stages of this process are:
+
         - Making the routing and placement of the circuit into the chip physical connectivity.
         - Translates the gates into the system native's gates (CZ, RZ, Drag, Wait and M (Measurement).
         - Converts the native gates to a pulse schedule using calibrated settings from the runcard.
 
         If ``optimize=True`` (default behaviour), then the transpilation also does some circuit optimization:
+
         - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
         - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).