Soc peripherals improvements

Bender.yml

@@ -14,40 +14,29 @@ package:
 
 dependencies:
   L2_tcdm_hybrid_interco: { git: "https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git", version: 1.0.0 }
-  apb:                    { git: "https://github.com/pulp-platform/apb.git", version:  0.1.0 }
+  apb:                    { git: "https://github.com/pulp-platform/apb.git", version:  0.2.2 }
   adv_dbg_if:             { git: "https://github.com/pulp-platform/adv_dbg_if.git", version: 0.0.2 }
   apb2per:                { git: "https://github.com/pulp-platform/apb2per.git", version: 0.1.0 }
   apb_adv_timer:          { git: "https://github.com/pulp-platform/apb_adv_timer.git", version: 1.0.4 }
-  apb_fll_if:             { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.1.3 }
-  apb_gpio:               { git: "https://github.com/pulp-platform/apb_gpio.git", rev: "0e9f142f2f11278445c953ad011fce1c7ed85b66" }
-  apb_node:               { git: "https://github.com/pulp-platform/apb_node.git", version: 0.1.1 }
-  apb_interrupt_cntrl:    { git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git", version: 0.1.1 }
-  axi:                    { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 }
+  apb_fll_if:             { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.2.0 }
+  apb_interrupt_cntrl:    { git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git", version: 0.2.0 }
+  axi:                    { git: "https://github.com/pulp-platform/axi.git", version: 0.38.0 }
   # axi_node:               { git: "https://github.com/pulp-platform/axi_node.git", version: 1.1.4 } # deprecated, replaced by axi_xbar (in axi repo)
   axi_slice:              { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo)
   timer_unit:             { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
   common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
   cluster_interconnect:   { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.1.1 }
   fpnew:                  { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.6 }
-  jtag_pulp:              { git: "https://github.com/pulp-platform/jtag_pulp.git", rev: v0.2.0 }
+  jtag_pulp:              { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 }
   cv32e40p:               { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "pulpissimo-v4.1.0"}
   ibex:                   { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" }
   scm:                    { git: "https://github.com/pulp-platform/scm.git", version: 1.0.1}
-  generic_FLL:            { git: "https://github.com/pulp-platform/generic_FLL.git", rev: "1c92dc73a940392182fd4cb7b86f35649b349595" }
+  generic_FLL:            { git: "https://github.com/pulp-platform/generic_FLL.git", version: 0.2.0 }
   tech_cells_generic:     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
-  udma_core:              { git: "https://github.com/pulp-platform/udma_core.git", version: 1.1.2 }
-  udma_uart:              { git: "https://github.com/pulp-platform/udma_uart.git", version: 1.0.2 }
-  udma_i2c:               { git: "https://github.com/pulp-platform/udma_i2c.git", version: 2.0.0 }
-  udma_i2s:               { git: "https://github.com/pulp-platform/udma_i2s.git", version: 1.1.2 }
-  udma_qspi:              { git: "https://github.com/pulp-platform/udma_qspi.git", version: 1.0.4 }
-  udma_sdio:              { git: "https://github.com/pulp-platform/udma_sdio.git", version: 1.1.2 }
-  udma_camera:            { git: "https://github.com/pulp-platform/udma_camera.git", version: 1.1.2 }
-  udma_filter:            { git: "https://github.com/pulp-platform/udma_filter.git", version: 1.0.3 }
-  udma_external_per:      { git: "https://github.com/pulp-platform/udma_external_per.git", version: 1.0.4 }
-  udma_hyper:             { git: "https://github.com/pulp-platform/udma_hyper.git", rev: "83ab704f9d1c5f9e5353268c901fe95c36bcea36" }
+  pulp_io:                { git: "https://github.com/pulp-platform/pulp-io.git", rev: v0.1.0-draft }
   hwpe-mac-engine:        { git: "https://github.com/pulp-platform/hwpe-mac-engine.git", version: 1.3.3 }
   riscv-dbg:              { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.5.0 }
-  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
+  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.2 }
 
 sources:
   # pulp_soc
@@ -63,19 +52,15 @@ sources:
       - rtl/pulp_soc/boot_rom.sv
       - rtl/pulp_soc/l2_ram_multi_bank.sv
       - rtl/pulp_soc/lint_jtag_wrap.sv
-      - rtl/pulp_soc/periph_bus_wrap.sv
-      - rtl/pulp_soc/soc_clk_rst_gen.sv
       - rtl/pulp_soc/soc_event_arbiter.sv
       - rtl/pulp_soc/soc_event_generator.sv
       - rtl/pulp_soc/soc_event_queue.sv
       - rtl/pulp_soc/tcdm_error_slave.sv
       - rtl/pulp_soc/soc_interconnect.sv
       - rtl/pulp_soc/soc_interconnect_wrap.sv
       - rtl/pulp_soc/soc_peripherals.sv
+      - rtl/pulp_soc/jtag_tap_top.sv
       - rtl/pulp_soc/pulp_soc.sv
-  # udma_subsystem
-  - files:
-      - rtl/udma_subsystem/udma_subsystem.sv
   # fc
   - target: rtl
     defines:

rtl/components/apb_soc_ctrl.sv

@@ -77,7 +77,7 @@ module apb_soc_ctrl #(
     output logic                      PREADY,
     output logic                      PSLVERR,
 
-    input  logic                      sel_fll_clk_i,
+    input  logic                      sel_pll_clk_i,
     input  logic                      boot_l2_i,
     input  logic [1:0]                bootsel_i,
     input  logic                      fc_fetch_en_valid_i,
@@ -485,7 +485,7 @@ module apb_soc_ctrl #(
           `REG_BOOTSEL:
             PRDATA =  {30'h0, r_bootsel};
           `REG_CLKSEL:
-            PRDATA = {31'h0,sel_fll_clk_i};
+            PRDATA = {31'h0,sel_pll_clk_i};
           `REG_CLUSTER_CTRL:
             PRDATA = {
               29'h0,

rtl/components/tb_fs_handler.sv

@@ -338,7 +338,7 @@ module tb_fs_handler_debug #(
 
           if (SILENT_MODE == "OFF") begin
             if (FULL_LINE == "ON") begin
-              $display("[STDOUT-CL%0d_PE%0d] %s", CLUSTER_ID, core_index,
+              $display("[STDOUT-CL%0d_PE%0d, %t] %s", CLUSTER_ID, core_index, $realtime,
                        LINE_BUFFER[core_index].substr(0, LINE_BUFFER[core_index].len() - 2));
               LINE_BUFFER[core_index] = "";
             end else begin

rtl/fc/fc_hwpe.sv

@@ -21,7 +21,7 @@ module fc_hwpe
     input  logic         test_mode_i,
 
     XBAR_TCDM_BUS.Master hwacc_xbar_master[N_MASTER_PORT-1:0],
-    APB_BUS.Slave        hwacc_cfg_slave,
+    APB.Slave            hwacc_cfg_slave,
 
     output logic [1:0]   evt_o,
     output logic         busy_o

rtl/fc/fc_subsystem.sv

@@ -33,8 +33,8 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #(
     XBAR_TCDM_BUS.Master              l2_data_master,
     XBAR_TCDM_BUS.Master              l2_instr_master,
     XBAR_TCDM_BUS.Master              l2_hwpe_master [NB_HWPE_PORTS-1:0],
-    APB_BUS.Slave                     apb_slave_eu,
-    APB_BUS.Slave                     apb_slave_hwpe,
+    APB.Slave                         apb_slave_eu,
+    APB.Slave                         apb_slave_hwpe,
 
     input  logic                      fetch_en_i,
     input  logic [31:0]               boot_addr_i,
@@ -43,7 +43,7 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #(
     input  logic                      event_fifo_valid_i,
     output logic                      event_fifo_fulln_o,
     input  logic [EVENT_ID_WIDTH-1:0] event_fifo_data_i, // goes indirectly to core interrupt
-    input  logic [31:0]               events_i, // goes directly to core interrupt, should be called irqs
+    input  logic [31:0]               interrupts_i, // goes directly to core interrupt, should be called irqs
     output logic [1:0]                hwpe_events_o,
 
     output logic                      supervisor_mode_o
@@ -330,7 +330,7 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #(
         .clk_i              ( clk_i              ),
         .rst_ni             ( rst_ni             ),
         .test_mode_i        ( test_en_i          ),
-        .events_i           ( events_i           ),
+        .events_i           ( interrupts_i       ),
         .event_fifo_valid_i ( event_fifo_valid_i ),
         .event_fifo_fulln_o ( event_fifo_fulln_o ),
         .event_fifo_data_i  ( event_fifo_data_i  ),

rtl/pulp_soc/boot_rom.sv

@@ -42,7 +42,10 @@ module boot_rom #(
 
         generic_rom #(
             .ADDR_WIDTH(ROM_ADDR_WIDTH-2), //The ROM uses 32-bit word addressing while the bus addresses bytes
-            .DATA_WIDTH(32)
+            .DATA_WIDTH(32),
+            .FILE_NAME("./boot/boot_code.cde") // CDE file is looked for in a
+                                              // folder relative to the
+                                              // simulation folder.
          ) rom_mem_i (
             .CLK            (  clk_i                ),
             .CEN            (  ~mem_slave.req        ),

rtl/pulp_soc/jtag_tap_top.sv

@@ -0,0 +1,119 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+
+module jtag_tap_top #(
+    parameter logic [31:0] IDCODE_VALUE = 32'h10000db3
+)(
+    input  logic              tck_i,
+    input  logic              trst_ni,
+    input  logic              tms_i,
+    input  logic              td_i,
+    output logic              td_o,
+
+    input  logic              test_clk_i,
+    input  logic              test_rstn_i,
+
+    input  logic        [7:0] soc_jtag_reg_i,
+    output logic        [7:0] soc_jtag_reg_o,
+    output logic              sel_fll_clk_o,
+
+   // tap
+   output logic               jtag_shift_dr_o,
+   output logic               jtag_update_dr_o,
+   output logic               jtag_capture_dr_o,
+   output logic               axireg_sel_o,
+
+   output logic               dbg_axi_scan_in_o,
+   input  logic               dbg_axi_scan_out_i
+);
+
+    logic                       s_scan_i;
+    logic [8:0]                 s_confreg;
+    logic                       confscan;
+    logic                       confreg_sel;
+    logic                       td_o_int;
+
+    logic [7:0] r_soc_reg0;
+    logic [7:0] r_soc_reg1;
+
+    logic [7:0] s_soc_jtag_reg_sync;
+
+
+
+    // jtag tap controller
+    tap_top  #(
+        .IDCODE_VALUE      ( IDCODE_VALUE       )
+    ) tap_top_i (
+        .tms_i             ( tms_i              ),
+        .tck_i             ( tck_i              ),
+        .rst_ni            ( trst_ni            ),
+        .td_i              ( td_i               ),
+        .td_o              ( td_o               ),
+
+        .shift_dr_o        ( jtag_shift_dr_o    ),
+        .update_dr_o       ( jtag_update_dr_o   ),
+        .capture_dr_o      ( jtag_capture_dr_o  ),
+
+        .memory_sel_o      ( axireg_sel_o       ),
+        .fifo_sel_o        (                    ),
+        .confreg_sel_o     ( confreg_sel        ),
+        .observ_sel_o      (                    ),
+        .clk_byp_sel_o     (                    ),
+
+        .scan_in_o         ( s_scan_i           ),
+
+        .observ_out_i      ( 1'b0               ),
+        .clk_byp_out_i     ( 1'b0               ),
+        .memory_out_i      ( dbg_axi_scan_out_i ),
+        .fifo_out_i        ( 1'b0               ),
+        .confreg_out_i     ( confscan           )
+    );
+
+    // pulp configuration register
+    jtagreg
+    #(
+        .JTAGREGSIZE(9),
+        .SYNC(0)
+    )
+    confreg
+    (
+        .clk_i                  ( tck_i               ),
+        .rst_ni                 ( trst_ni             ),
+        .enable_i               ( confreg_sel         ),
+        .capture_dr_i           ( jtag_capture_dr_o   ),
+        .shift_dr_i             ( jtag_shift_dr_o     ),
+        .update_dr_i            ( jtag_update_dr_o    ),
+        .jtagreg_in_i           ( {1'b0, s_soc_jtag_reg_sync} ), //at sys rst enable the fll
+        .mode_i                 ( 1'b1                ),
+        .scan_in_i              ( s_scan_i            ),
+        .jtagreg_out_o          ( s_confreg           ),
+        .scan_out_o             ( confscan            )
+    );
+
+    always_ff @(posedge tck_i or negedge trst_ni) begin
+      if(~trst_ni) begin
+        r_soc_reg0 <= 0;
+        r_soc_reg1 <= 0;
+      end else begin
+        r_soc_reg1 <= soc_jtag_reg_i;
+        r_soc_reg0 <= r_soc_reg1;
+      end
+    end
+
+   assign s_soc_jtag_reg_sync =r_soc_reg0;
+
+   assign dbg_axi_scan_in_o           =  s_scan_i;
+
+   assign soc_jtag_reg_o              =  s_confreg[7:0];
+
+   assign sel_fll_clk_o               =  s_confreg[8];
+
+endmodule