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Add OS support to Ara #61

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Commits on Oct 15, 2024

  1. [RVV] Add prototypical extension to instruction tracer (vld, vst)

    @MaistoV @mp-17
    MaistoV authored and mp-17 committed Oct 15, 2024
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  2. [ARA] Propagating exception from accelerator

    @MaistoV @mp-17
    MaistoV authored and mp-17 committed Oct 15, 2024
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  3. acc: add mmu interface for accelerator

    @mp-17
    mp-17 committed Oct 15, 2024
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  4. lsu: add MMU accelerator port

    @mp-17
    mp-17 committed Oct 15, 2024
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  5. acc_dispatcher: align signal names with new nomenclature

    @mp-17
    mp-17 committed Oct 15, 2024
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  6. acc_dispatcher: don't issue instruction from buffer if flushing 

    Instructions with side effects flush the unissued instructions from
the controller. The accelerator dispatcher buffer is flushed when
this happens and avoids accepting a new instruction, but was not
preventing the actual issue during a flush cycle.
    @mp-17
    mp-17 committed Oct 15, 2024
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Commits on Nov 7, 2024

  1. acc_dispatcher: cut instruction dispatch path from CVA6 to Ara

    @mp-17
    mp-17 committed Nov 7, 2024
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