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WB cache miss handler: fixes
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ezelioli committed Jun 6, 2024
1 parent f470b86 commit 86e4d1d
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions core/cache_subsystem/miss_handler.sv
Original file line number Diff line number Diff line change
Expand Up @@ -257,7 +257,7 @@ module miss_handler
state_d = AMO_WB;
serve_amo_d = 1'b1;
cnt_d = '0;
req_o = 1'b1;
req_o = '1;
addr_o = amo_req_i.operand_a;
end
// check if we want to flush and can flush e.g.: we are not busy anymore
Expand Down Expand Up @@ -301,7 +301,7 @@ module miss_handler
mshr_d.be = miss_req_be[i];
mshr_d.make_unique = 1'b0;
req_o = '1;
addr_o = mshr_q.addr[DCACHE_INDEX_WIDTH-1:0];
addr_o = mshr_d.addr[DCACHE_INDEX_WIDTH-1:0];
miss_o = 1'b1;
break;
end
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