Reparametrize WB-cache multiple outstanding stores

Split parametrization of multiple outstanding stores towards cached and un-cached addresses.
pulp-platform · May 22, 2024 · 4175909 · 4175909
1 parent 15baec9
commit 4175909
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Showing 23 changed files with 57 additions and 25 deletions.
diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv
@@ -23,6 +23,7 @@ module axi_adapter #(
     parameter int unsigned DATA_WIDTH = 256,
     parameter logic        CRITICAL_WORD_FIRST   = 0, // the AXI subsystem needs to support wrapping reads for this feature
     parameter int unsigned CACHELINE_BYTE_OFFSET = 8,
+    parameter int unsigned MAX_OUTSTANDING_AW    = 0, // Actual number of in-flight store transactions allowed is (MAX_OUTSTANDING_AW+1)
     parameter logic        AXI_ACE               = 0, // Support AMBA ACE
     parameter type axi_req_t = logic,
     parameter type axi_rsp_t = logic
@@ -61,7 +62,6 @@ module axi_adapter #(
   ) > 0) ? $clog2(
       DATA_WIDTH / CVA6Cfg.AxiDataWidth
   ) : 1;
-  localparam MAX_OUTSTANDING_AW = CVA6Cfg.MaxOutstandingStores;
   localparam MAX_OUTSTANDING_AW_CNT_WIDTH = $clog2(
       MAX_OUTSTANDING_AW + 1
   ) > 0 ? $clog2(

diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv
@@ -741,7 +741,7 @@ module miss_handler
   // ----------------------
   axi_adapter_arbiter #(
       .NR_PORTS           (NR_BYPASS_PORTS),
-      .MAX_OUTSTANDING_REQ(CVA6Cfg.MaxOutstandingStores),
+      .MAX_OUTSTANDING_REQ(CVA6Cfg.MaxOutstandingUncachedStores),
       .req_t              (bypass_req_t),
       .rsp_t              (bypass_rsp_t)
   ) i_bypass_arbiter (
@@ -767,6 +767,7 @@ module miss_handler
       .CVA6Cfg              (CVA6Cfg),
       .DATA_WIDTH           (64),
       .CACHELINE_BYTE_OFFSET(DCACHE_BYTE_OFFSET),
+      .MAX_OUTSTANDING_AW   (CVA6Cfg.MaxOutstandingUncachedStores),
       .AXI_ACE              (DCACHE_COHERENT),
       .axi_req_t            (axi_req_t),
       .axi_rsp_t            (axi_rsp_t)
@@ -808,6 +809,7 @@ module miss_handler
       .CVA6Cfg              (CVA6Cfg),
       .DATA_WIDTH           (DCACHE_LINE_WIDTH),
       .CACHELINE_BYTE_OFFSET(DCACHE_BYTE_OFFSET),
+      .MAX_OUTSTANDING_AW   (CVA6Cfg.MaxOutstandingCachedStores),
       .AXI_ACE              (DCACHE_COHERENT),
       .axi_req_t            (axi_req_t),
       .axi_rsp_t            (axi_rsp_t)

diff --git a/core/cva6.sv b/core/cva6.sv
@@ -245,7 +245,8 @@ module cva6
     CVA6Cfg.NrSharedRegionRules,
     CVA6Cfg.SharedRegionAddrBase,
     CVA6Cfg.SharedRegionLength,
-    CVA6Cfg.MaxOutstandingStores,
+    CVA6Cfg.MaxOutstandingCachedStores,
+    CVA6Cfg.MaxOutstandingUncachedStores,
     CVA6Cfg.DebugEn,
     NonIdemPotenceEn,
     CVA6Cfg.AxiBurstWriteEn

diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv
@@ -114,7 +114,8 @@ module cva6_rvfi
     CVA6Cfg.NrCachedRegionRules,
     CVA6Cfg.CachedRegionAddrBase,
     CVA6Cfg.CachedRegionLength,
-    CVA6Cfg.MaxOutstandingStores,
+    CVA6Cfg.MaxOutstandingCachedStores,
+    CVA6Cfg.MaxOutstandingUncachedStores,
     CVA6Cfg.DebugEn,
     NonIdemPotenceEn,
     CVA6Cfg.AxiBurstWriteEn

diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv
@@ -156,8 +156,15 @@ package config_pkg;
     logic [NrMaxRules-1:0][63:0] SharedRegionAddrBase;
     // bit mask which bits to consider when matching the rule
     logic [NrMaxRules-1:0][63:0] SharedRegionLength;
-    // Maximum number of outstanding stores
-    int unsigned                 MaxOutstandingStores;
+    // Maximum number of outstanding stores towards **cached** addresses
+    // NOTE: This parameters allows to have multiple inflight write transactions (if set > 0)
+    //       Setting this parameter to **0** allows only one inflight write transaction towards memory.
+    // IMPORTANT: This parameter currently **must be fixed to 0** for cache-coherent configurations (CVA6ConfigDcacheCoherent == 1)
+    int unsigned                 MaxOutstandingCachedStores;
+    // Maximum number of outstanding stores towards **uncached** addresses
+    // NOTE: This parameters allows to have multiple inflight write transactions (if set > 0)
+    //       Setting this parameter to **0** allows only one inflight write transaction towards memory.
+    int unsigned                 MaxOutstandingUncachedStores;
     // Debug support
     bit                          DebugEn;
     // Non idem potency

diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv
@@ -136,7 +136,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(0),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv
@@ -157,7 +157,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(0),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -165,7 +165,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
@@ -161,7 +161,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
@@ -161,7 +161,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv b/core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -158,7 +158,8 @@ package cva6_config_pkg;
       ),
       SharedRegionAddrBase: 1024'({64'h8000_0000}),
       SharedRegionLength: 1024'({64'h40000000}),
-      MaxOutstandingStores: unsigned'(7),
+      MaxOutstandingCachedStores: unsigned'(0),
+      MaxOutstandingUncachedStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv
@@ -214,7 +214,8 @@ localparam config_pkg::cva6_cfg_t CVA6Cfg = '{
   NrCachedRegionRules:   unsigned'(1),
   CachedRegionAddrBase:  1024'({ariane_soc::DRAMBase}),
   CachedRegionLength:    1024'({ariane_soc::DRAMLength}),
-  MaxOutstandingStores:  unsigned'(7),
+  MaxOutstandingCachedStores:  unsigned'(0),
+  MaxOutstandingUncachedStores:  unsigned'(7),
   DebugEn: bit'(1),
   NonIdemPotenceEn: bit'(0),
   AxiBurstWriteEn: bit'(0)

diff --git a/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst b/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst
@@ -228,8 +228,12 @@
      - PMA cache region rules
      - {64'h40000000}
 
-   * - MaxOutstandingStores
-     - Maximum number of outstanding stores
+   * - MaxOutstandingCachedStores
+     - Maximum number of outstanding stores towards cached regions
+     - 0
+
+   * - MaxOutstandingUncachedStores
+     - Maximum number of outstanding stores towards uncached regions
      - 7
 
    * - DebugEn