Add error correction to TLB (only SV39x4).

pulp-platform · May 27, 2024 · 25c431b · 25c431b
1 parent 2f0d702
commit 25c431b
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Showing 6 changed files with 183 additions and 68 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -13,6 +13,8 @@ dependencies:
   fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.1 }
   tech_cells_generic:
     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
+  redundancy_cells:
+    { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: "c44ff735" } # branch: astral-v0
 
 frozen: true
 

diff --git a/core/cva6.sv b/core/cva6.sv
@@ -20,6 +20,7 @@ module cva6
     // CVA6 config
     parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
     parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace),
+    parameter bit EccEnable = 1'b0,
     // RVFI
     parameter type rvfi_probes_t = struct packed {
       logic [TRANS_ID_BITS-1:0]                                               issue_pointer;
@@ -745,7 +746,8 @@ module cva6
   ex_stage #(
       .CVA6Cfg   (CVA6ExtendCfg),
       .ASID_WIDTH(ASID_WIDTH),
-      .VMID_WIDTH(VMID_WIDTH)
+      .VMID_WIDTH(VMID_WIDTH),
+      .EccEnable (EccEnable)
   ) ex_stage_i (
       .clk_i(clk_i),
       .rst_ni(rst_uarch_n),

diff --git a/core/ex_stage.sv b/core/ex_stage.sv
@@ -20,7 +20,8 @@ module ex_stage
 #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
     parameter int unsigned ASID_WIDTH = 1,
-    parameter int unsigned VMID_WIDTH = 1
+    parameter int unsigned VMID_WIDTH = 1,
+    parameter bit          EccEnable  = 1'b0
 ) (
     // Subsystem Clock - SUBSYSTEM
     input  logic                                                        clk_i,
@@ -411,7 +412,8 @@ module ex_stage
   load_store_unit #(
       .CVA6Cfg   (CVA6Cfg),
       .ASID_WIDTH(ASID_WIDTH),
-      .VMID_WIDTH(VMID_WIDTH)
+      .VMID_WIDTH(VMID_WIDTH),
+      .EccEnable (EccEnable)
   ) lsu_i (
       .clk_i,
       .rst_ni,

diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv
@@ -19,7 +19,8 @@ module load_store_unit
 #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
     parameter int unsigned ASID_WIDTH = 1,
-    parameter int unsigned VMID_WIDTH = 1
+    parameter int unsigned VMID_WIDTH = 1,
+    parameter bit          EccEnable  = 1'b0
 ) (
     // Subsystem Clock - SUBSYSTEM
     input logic clk_i,
@@ -214,7 +215,8 @@ module load_store_unit
         .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
         .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
         .ASID_WIDTH       (ASID_WIDTH),
-        .VMID_WIDTH       (VMID_WIDTH)
+        .VMID_WIDTH       (VMID_WIDTH),
+        .EccEnable        (EccEnable)
     ) i_cva6_mmu (
         // misaligned bypass
         .misaligned_ex_i(misaligned_exception),

diff --git a/core/mmu_sv39x4/cva6_mmu_sv39x4.sv b/core/mmu_sv39x4/cva6_mmu_sv39x4.sv
@@ -27,7 +27,8 @@ module cva6_mmu_sv39x4
     parameter int unsigned           INSTR_TLB_ENTRIES = 4,
     parameter int unsigned           DATA_TLB_ENTRIES  = 4,
     parameter int unsigned           ASID_WIDTH        = 1,
-    parameter int unsigned           VMID_WIDTH        = 1
+    parameter int unsigned           VMID_WIDTH        = 1,
+    parameter bit                    EccEnable         = 1'b0
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -140,7 +141,8 @@ module cva6_mmu_sv39x4
       .CVA6Cfg    (CVA6Cfg),
       .TLB_ENTRIES(INSTR_TLB_ENTRIES),
       .ASID_WIDTH (ASID_WIDTH),
-      .VMID_WIDTH (VMID_WIDTH)
+      .VMID_WIDTH (VMID_WIDTH),
+      .EccEnable  (EccEnable)
   ) i_itlb (
       .clk_i       (clk_i),
       .rst_ni      (rst_ni),
@@ -175,7 +177,8 @@ module cva6_mmu_sv39x4
       .CVA6Cfg    (CVA6Cfg),
       .TLB_ENTRIES(DATA_TLB_ENTRIES),
       .ASID_WIDTH (ASID_WIDTH),
-      .VMID_WIDTH (VMID_WIDTH)
+      .VMID_WIDTH (VMID_WIDTH),
+      .EccEnable  (EccEnable)
   ) i_dtlb (
       .clk_i       (clk_i),
       .rst_ni      (rst_ni),