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lint: Fix upstream verilog lint issues
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paulsc96 committed Nov 6, 2024
1 parent 36dd59a commit 01e8b1e
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Showing 2 changed files with 12 additions and 12 deletions.
10 changes: 5 additions & 5 deletions core/cache_subsystem/std_cache_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,7 @@ module std_cache_subsystem
.flush_i (1'b0),
.testmode_i(1'b0),
.full_o (w_fifo_full),
.empty_o (), // leave open
.empty_o (), // leave open
.usage_o (w_fifo_usage),
.data_i (w_select),
// a new transaction was requested and granted
Expand All @@ -218,14 +218,14 @@ module std_cache_subsystem
.pop_i (w_fifo_pop)
);

always_ff @( posedge clk_i or negedge rst_ni ) begin : aw_lock_reg
always_ff @(posedge clk_i or negedge rst_ni) begin : aw_lock_reg
if (~rst_ni) aw_lock_q <= 1'b0;
else aw_lock_q <= aw_lock_d;
else aw_lock_q <= aw_lock_d;
end

assign w_fifo_push = ~aw_lock_q & axi_req_o.aw_valid;
assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last;
assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q);
assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last;
assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q);

// In fall-through mode, the empty_o will be low when push_i is high (on zero usage).
// We do not want this here. Also, usage_o is missing the MSB, so on full fifo, usage_o is zero.
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14 changes: 7 additions & 7 deletions core/cache_subsystem/tag_cmp.sv
Original file line number Diff line number Diff line change
Expand Up @@ -85,13 +85,13 @@ module tag_cmp #(

`ifndef SYNTHESIS
`ifndef VERILATOR
// assert that cache only hits on one way
// this only needs to be checked one cycle after all ways have been requested
onehot :
assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
else begin
$fatal(1, "Hit should be one-hot encoded");
end
// assert that cache only hits on one way
// this only needs to be checked one cycle after all ways have been requested
onehot :
assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
else begin
$fatal(1, "Hit should be one-hot encoded");
end
`endif
`endif

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