Integrate Culsans on top of Astral modifications. #129
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linker script made non-SMP core push funky values in the SP resulting in accesses to undefined memory regions that lead to illegal instructions (and the test hanged). Tested on a simple dual-core hello world.
garbage in SP address.
not lose info stored in the dcaches.
added 14 commits
June 19, 2024 14:12
Aquaticfuller
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Jul 16, 2024
Point to open-source deps - 2
disabling all AXI masters except the cores.
…140) * Properly connect output AXI bus if no redundancy is enabled. * Bump CVA6 for ECC in TLB. * Bump CVA6 to extend ECC also in TLB tags. * Bump CVA6. * Bump CVA6 to optimize ECC encoders in TLB. * IOMMU Integration (#126) * Bump CVA6. * Bump CVA6. * IOMMU integration. Integration of IOMMU and its software libraries as git submodule. Introduced 4 irq line dedicated to IOMMU. Updated idma test to config IOMMU in bare mode. Regenerate PLIC accordingly. * Bump IOMMU with err-slv fix --------- Co-authored-by: Yvan Tortorella <[email protected]> Co-authored-by: Your Name <[email protected]> * Add ECC axi_llc (single error handling) to astral-v0 cheshire (#137) * Integrate HMR unit for CVA6 redundancy. * Initial ecc llc cheshire integration * update the axi_llc and redundancy_cells dependency * Update axi_llc and redundancy_cells deps, axi_llc now reports ecc scrubber uncorrectable error to cheshire * Update the axi_llc and redundancy_cells, the redundancy_cells has rebased to the master branch * Update axi_llc dep * Update axi_llc dep, fix a parameter issue for synthesis * [BENDER] Update the axi_llc and redundancy_cells dependencies, the timing cut version. * [BENDER] Update axi_llc dep. --------- Co-authored-by: Yvan Tortorella <[email protected]> * Bump `cva6` --------- Co-authored-by: Yvan Tortorella <[email protected]> Co-authored-by: Maicol Ciani <[email protected]> Co-authored-by: Your Name <[email protected]> Co-authored-by: zexinfu <[email protected]>
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