fpga: Adding vcu118 BD support

pulp-platform · Jul 8, 2024 · 9a049ce · 9a049ce
1 parent 48185f6
commit 9a049ce
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Showing 14 changed files with 693 additions and 13 deletions.
diff --git a/sw/boot/carfield_bd_vcu128.dts → sw/boot/carfield_bd.dts b/sw/boot/carfield_bd_vcu128.dts → sw/boot/carfield_bd.dts
diff --git a/sw/boot/carfield_vanilla_vcu128.dts → sw/boot/carfield_vanilla.dts b/sw/boot/carfield_vanilla_vcu128.dts → sw/boot/carfield_vanilla.dts
diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc
@@ -0,0 +1,40 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
+# VIOs are asynchronous
+set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
+
+# Create system clocks
+create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+
+# PCIe clock LOC
+#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]]
+#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]]
+
+set_property PACKAGE_PIN AW25     [get_ports "uart_rx_i"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rx_i"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
+set_property PACKAGE_PIN BB21     [get_ports "uart_tx_o"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_tx_o"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
+#set_property PACKAGE_PIN BB22     [get_ports "uart_rts_o"] ;
+#set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rts_o"] ;
+#set_property PACKAGE_PIN AY25     [get_ports "uart_cts_i"] ;
+#set_property IOSTANDARD  LVCMOS18 [get_ports "uart_cts_i"] ;
+
+set_property PACKAGE_PIN L19      [get_ports cpu_reset] ;# Bank  73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
+set_property IOSTANDARD  LVCMOS12 [get_ports cpu_reset] ;# Bank  73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
+
+set_property BOARD_PART_PIN default_250mhz_clk1_n [get_ports default_250mhz_clk1_clk_n]
+set_property BOARD_PART_PIN default_250mhz_clk1_p [get_ports default_250mhz_clk1_clk_p]
+
+set_property PACKAGE_PIN D12      [get_ports default_250mhz_clk1_clk_n]    ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
+set_property IOSTANDARD  DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_n] ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
+set_property PACKAGE_PIN E12      [get_ports default_250mhz_clk1_clk_p]    ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
+set_property IOSTANDARD  DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_p] ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
diff --git a/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc
@@ -0,0 +1,17 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+#
+set_property PACKAGE_PIN N30     [get_ports jtag_tdo_o]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdo_o]
+
+set_property PACKAGE_PIN P30     [get_ports jtag_tck_i]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tck_i]
+
+set_property PACKAGE_PIN N28     [get_ports jtag_tms_i]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tms_i]
+
+set_property PACKAGE_PIN M30     [get_ports jtag_tdi_i]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdi_i]
diff --git a/target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc
@@ -0,0 +1,59 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
+
+# (FMCP_HSPC_LA13_N)
+set_property PACKAGE_PIN AJ36     [get_ports "pad_hyper_csn[1]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43
+
+# (FMCP_HSPC_LA13_P)
+set_property PACKAGE_PIN AJ35     [get_ports "pad_hyper_csn[0]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43
+
+# (FMCP_HSPC_LA14_P)
+set_property PACKAGE_PIN AG31     [get_ports "pad_hyper_rwds"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_rwds"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43
+
+# (FMCP_HSPC_LA09_N)
+set_property PACKAGE_PIN AK33     [get_ports "pad_hyper_dq[2]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[2]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43
+
+# (FMCP_HSPC_LA10_N)
+set_property PACKAGE_PIN AR35     [get_ports "pad_hyper_dq[3]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[3]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43
+
+# (FMCP_HSPC_LA10_P)
+set_property PACKAGE_PIN AP35     [get_ports "pad_hyper_dq[0]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[0]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43
+
+# (FMCP_HSPC_LA09_P)
+set_property PACKAGE_PIN AJ33     [get_ports "pad_hyper_dq[4]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43
+
+# (FMCP_HSPC_LA06_N)
+set_property PACKAGE_PIN AT36     [get_ports "pad_hyper_dq[7]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43
+
+# (FMCP_HSPC_LA06_P)
+set_property PACKAGE_PIN AT35     [get_ports "pad_hyper_dq[1]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43
+
+# (FMCP_HSPC_LA01_CC_N)
+set_property PACKAGE_PIN AL31     [get_ports "pad_hyper_ckn"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_ckn"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43
+
+# (FMCP_HSPC_LA01_CC_P)
+set_property PACKAGE_PIN AL30     [get_ports "pad_hyper_ck"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_ck"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43
+
+# (FMCP_HSPC_LA05_N)
+set_property PACKAGE_PIN AR38     [get_ports "pad_hyper_dq[5]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43
+
+# (FMCP_HSPC_LA05_P)
+set_property PACKAGE_PIN AP38     [get_ports "pad_hyper_dq[6]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43
+set_property IOSTANDARD  LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# Bank  43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43
diff --git a/target/xilinx/flavor_bd/constraints/vcu128.xdc b/target/xilinx/flavor_bd/constraints/vcu128.xdc
@@ -1,3 +1,9 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
 # VIOs are asynchronous
 set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
 

diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc
@@ -1,4 +1,4 @@
-# Copyright 2020 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

diff --git a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc
@@ -1,4 +1,4 @@
-# Copyright 2020 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk
@@ -49,6 +49,6 @@ $(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor
 .PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit
 
 car-xil-clean-bd:
-	cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/
+	cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_* .Xil/
 
 .PHONY: car-xil-clean-bd
diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl
@@ -4,15 +4,12 @@
 #
 # Cyril Koenig <[email protected]>
 
-set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ]
 set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ]
 set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ]
 set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ]
 set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ]
-set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ]
-connect_bd_net -net carfield_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_gnd_o]
+
 connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o]
-connect_bd_net -net carfield_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_vdd_o]
 connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i]
 connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i]
 connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i]