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Fix configurable top level bugs and integrate CI flow. (#2)
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* Bump dependencies and align testbench with new Cheshire JTAG tasks.

* Fix connections.

* Align cache-enable CSR with OpenHW recent changes...

* Add draft CI flow.

* Use normal printf in `Helloworld`.

* Update nonfree rules.

* Fix parameter declaration in L2 Ecc asyncronoys buses.

* Fix PULP cluster EOC and busy enable connections.

* Update nonfree.

* Bump nonfree.

* Bump nonfree to copy uImage in dedicated `astral` folder.

* Apply suggestions from code review

Co-authored-by: Michael Rogenmoser <[email protected]>

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Co-authored-by: Yvan Tortorella <[email protected]>
Co-authored-by: Michael Rogenmoser <[email protected]>
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3 people committed Aug 3, 2024
1 parent 1a69d70 commit ebdce0e
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4 changes: 1 addition & 3 deletions hw/carfield.sv
Original file line number Diff line number Diff line change
Expand Up @@ -669,7 +669,7 @@ for (genvar i=0; i<NumSyncRegSlv; i++ ) begin : gen_chs_ext_reg_cut
);
end

// Passsing the `ext_reg_req_cut[CarfieldRegBusSlvIdx.pcrs]` value to the
// Passing the `ext_reg_req_cut[CarfieldRegBusSlvIdx.pcrs]` value to the
// reg_req_i/rsp_o buses results in Questa's `Fatal: Unexpected signal: 11.`
// at compile time. Direct casting 'int(CarfieldRegBusSlvIdx.pcrs) also does
// not work resulting in the ext_reg_rsp_cut bus being all X. The localparam
Expand Down Expand Up @@ -1098,14 +1098,12 @@ if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2
.slvport_w_data_i ( axi_slv_ext_w_data [NumL2Ports-1:0] ),
.slvport_w_wptr_i ( axi_slv_ext_w_wptr [NumL2Ports-1:0] ),
.slvport_w_rptr_o ( axi_slv_ext_w_rptr [NumL2Ports-1:0] ),
// verilog_lint: waive-start line-length
.l2_ecc_reg_async_mst_req_i ( ext_reg_async_slv_req_out [EccAsyncIdx] ),
.l2_ecc_reg_async_mst_ack_o ( ext_reg_async_slv_ack_in [EccAsyncIdx] ),
.l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[EccAsyncIdx] ),
.l2_ecc_reg_async_mst_req_o ( ext_reg_async_slv_req_in [EccAsyncIdx] ),
.l2_ecc_reg_async_mst_ack_i ( ext_reg_async_slv_ack_out [EccAsyncIdx] ),
.l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [EccAsyncIdx] ),
// verilog_lint: waive-stop line-length
.ecc_error_o ( l2_ecc_err )
);
end else begin: gen_no_l2
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4 changes: 2 additions & 2 deletions target/sim/src/carfield_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -485,8 +485,8 @@ module tb_carfield_soc;
fix.chs_vip.jtag_elf_halt_load(spatzd_preload_elf, spatzd_binary_entry );

// write start address into the csr
$display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", SpatzClusterPeriphStartAddr + SpatzClusterPeripheralBootControlOffset, spatzd_binary_entry);
fix.chs_vip.jtag_write_reg32(SpatzClusterPeriphStartAddr + SpatzClusterPeripheralBootControlOffset, spatzd_binary_entry, jtag_check_write);
$display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry);
fix.chs_vip.jtag_write_reg32(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry, jtag_check_write);

// Set interrupt on mailbox mailbox id MBOX_SPATZD_CORE0_ID and MBOX_SPATZD_CORE1_ID
spatzd_reg_value = 64'h1;
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