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Fix linting errs
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Your Name committed Mar 19, 2024
1 parent e36e28e commit ddfa53d
Showing 1 changed file with 4 additions and 2 deletions.
6 changes: 4 additions & 2 deletions hw/carfield.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1759,7 +1759,8 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem
assign security_island_isolate_req = car_regs_reg2hw.security_island_isolate.q &&
!secure_boot_i;
assign car_regs_hw2reg.security_island_isolate_status.d =
master_isolated_rsp[SecurityIslandTlulMstIdx] & master_isolated_rsp[SecurityIslandiDMAMstIdx];
master_isolated_rsp[SecurityIslandTlulMstIdx]

Check warning on line 1762 in hw/carfield.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/carfield.sv#L1762 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/carfield.sv" range:{start:{line:1762 column:55}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1762 column:55} end:{line:1763}} text:"         master_isolated_rsp[SecurityIslandTlulMstIdx]\n"}
& master_isolated_rsp[SecurityIslandiDMAMstIdx];
assign car_regs_hw2reg.security_island_isolate_status.de = 1'b1;

typedef logic [Cfg.AddrWidth-1:0] narrow_axi_addr_t;
Expand Down Expand Up @@ -1855,7 +1856,8 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem
.async_idma_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SecurityIslandiDMAMstIdx] ),
.async_idma_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SecurityIslandiDMAMstIdx] ),
.axi_isolate_i ( security_island_isolate_req ),
.axi_isolated_o ( { master_isolated_rsp[SecurityIslandiDMAMstIdx], master_isolated_rsp[SecurityIslandTlulMstIdx] } ),
.axi_isolated_o ( { master_isolated_rsp[SecurityIslandiDMAMstIdx],
master_isolated_rsp[SecurityIslandTlulMstIdx] } ),
// Uart
.ibex_uart_rx_i ( uart_ot_rx_i ),
.ibex_uart_tx_o ( uart_ot_tx_o ),
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