Fix configurable top level bugs and integrate CI flow. (#2)

* Bump dependencies and align testbench with new Cheshire JTAG tasks. * Fix connections. * Align cache-enable CSR with OpenHW recent changes... * Add draft CI flow. * Use normal printf in `Helloworld`. * Update nonfree rules. * Fix parameter declaration in L2 Ecc asyncronoys buses. * Fix PULP cluster EOC and busy enable connections. * Update nonfree. * Bump nonfree. * Bump nonfree to copy uImage in dedicated `astral` folder. * Apply suggestions from code review Co-authored-by: Michael Rogenmoser <[email protected]> --------- Co-authored-by: Yvan Tortorella <[email protected]> Co-authored-by: Michael Rogenmoser <[email protected]>
pulp-platform · Jun 26, 2024 · 972f9d5 · 972f9d5
1 parent 84d14c2
commit 972f9d5
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diff --git a/Bender.lock b/Bender.lock
@@ -113,7 +113,7 @@ packages:
       Git: https://github.com/AlSaqr-platform/can_bus.git
     dependencies: []
   cheshire:
-    revision: d6274a52dab68d12765b64d670d528774eb36c2c
+    revision: 6d389373df6b54c09888f89411b7e231d2430722
     version: null
     source:
       Git: https://github.com/pulp-platform/cheshire.git
@@ -169,8 +169,13 @@ packages:
     dependencies:
     - hci
   common_cells:
+<<<<<<< HEAD
     revision: f4d6406070d8e7767e4e9a433f11b039859f03a1
     version: null
+=======
+    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
+    version: 1.33.0
+>>>>>>> 4c563a2 (Fix configurable top level bugs and integrate CI flow. (#2))
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -441,8 +446,13 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
+<<<<<<< HEAD
     revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
     version: 0.4.4
+=======
+    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
+    version: 0.4.3
+>>>>>>> 4c563a2 (Fix configurable top level bugs and integrate CI flow. (#2))
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -13,7 +13,7 @@ package:
 dependencies:
   register_interface: { git: https://github.com/pulp-platform/register_interface.git,   version: 0.4.3                                }
   axi:                { git: https://github.com/pulp-platform/axi.git,                  version: 0.39.1                               }
-  cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: d6274a52dab68d12765b64d670d528774eb36c2c } # branch: idma-rebase
+  cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: 6d389373df6b54c09888f89411b7e231d2430722 } # branch: astral-new
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh
   dyn_mem:            { git: https://github.com/pulp-platform/dyn_spm.git,              rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main
   safety_island:      { git: https://github.com/pulp-platform/safety_island.git,        rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield

diff --git a/hw/carfield.sv b/hw/carfield.sv
@@ -668,7 +668,7 @@ for (genvar i=0; i<NumSyncRegSlv; i++ ) begin : gen_chs_ext_reg_cut
   );
 end
 
-// Passsing the `ext_reg_req_cut[CarfieldRegBusSlvIdx.pcrs]` value to the
+// Passing the `ext_reg_req_cut[CarfieldRegBusSlvIdx.pcrs]` value to the
 // reg_req_i/rsp_o buses results in Questa's `Fatal: Unexpected signal: 11.`
 // at compile time. Direct casting 'int(CarfieldRegBusSlvIdx.pcrs) also does
 // not work resulting in the ext_reg_rsp_cut bus being all X. The localparam
@@ -1062,14 +1062,12 @@ if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2
     .slvport_w_data_i    ( axi_slv_ext_w_data  [NumL2Ports-1:0] ),
     .slvport_w_wptr_i    ( axi_slv_ext_w_wptr  [NumL2Ports-1:0] ),
     .slvport_w_rptr_o    ( axi_slv_ext_w_rptr  [NumL2Ports-1:0] ),
-    // verilog_lint: waive-start line-length
     .l2_ecc_reg_async_mst_req_i  ( ext_reg_async_slv_req_out [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_ack_o  ( ext_reg_async_slv_ack_in  [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_req_o  ( ext_reg_async_slv_req_in  [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_ack_i  ( ext_reg_async_slv_ack_out [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [EccAsyncIdx] ),
-    // verilog_lint: waive-stop line-length
     .ecc_error_o         ( l2_ecc_err                           )
   );
 end else begin: gen_no_l2

diff --git a/target/sim/src/carfield_tb.sv b/target/sim/src/carfield_tb.sv
@@ -484,8 +484,8 @@ module tb_carfield_soc;
             fix.chs_vip.jtag_elf_halt_load(spatzd_preload_elf, spatzd_binary_entry );
 
             // write start address into the csr
-            $display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", SpatzClusterPeriphStartAddr + SpatzClusterPeripheralBootControlOffset, spatzd_binary_entry);
-            fix.chs_vip.jtag_write_reg32(SpatzClusterPeriphStartAddr + SpatzClusterPeripheralBootControlOffset, spatzd_binary_entry, jtag_check_write);
+            $display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry);
+            fix.chs_vip.jtag_write_reg32(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry, jtag_check_write);
 
             // Set interrupt on mailbox mailbox id MBOX_SPATZD_CORE0_ID and MBOX_SPATZD_CORE1_ID
             spatzd_reg_value = 64'h1;