Integrate technology flow.

pulp-platform · Mar 3, 2024 · 583ae4d · 583ae4d
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commit 583ae4d
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Showing 9 changed files with 57 additions and 11 deletions.
diff --git a/Bender.local b/Bender.local
@@ -6,8 +6,8 @@ overrides:
   axi:                  { git: https://github.com/pulp-platform/axi.git                   , version: 0.39.1 }
   axi_riscv_atomics:    { git: https://github.com/pulp-platform/axi_riscv_atomics.git     , version: 0.8.2 }
   apb:                  { git: "https://github.com/pulp-platform/apb.git"                 , version: 0.2.3 }
-  register_interface:   { git: "https://github.com/pulp-platform/register_interface.git"  , version: 0.4.1 }
-  redundancy_cells:     { git: "https://github.com/pulp-platform/redundancy_cells.git"    , rev: "09cd9514d52145530fa432e6692ed33aec6c04b6" } # branch: astral
+  register_interface:   { git: "https://github.com/pulp-platform/register_interface.git"  , rev: "e4b20be8833180863ebc64675c93b1694239c505" } # branch: astral
+  redundancy_cells:     { git: "https://github.com/pulp-platform/redundancy_cells.git"    , rev: "3fbd080e479f194f68e51dbe262e62c4362868bd" } # branch: astral
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git"  , version: =0.2.13                                }
   riscv-dbg:            { git: "https://github.com/pulp-platform/riscv-dbg.git"           , version: =0.8.0                                 }
   idma:                 { git: "https://github.com/pulp-platform/idma.git"                , version: 0.5.1                                  }

diff --git a/Bender.lock b/Bender.lock
@@ -46,7 +46,7 @@ packages:
     dependencies:
     - axi_slice
   axi_llc:
-    revision: 76933aa7fa8ff5c8ccbc075f6af4fca4d8416d17
+    revision: d79a00b8673b814efacbbe9bf106103407fc401b
     version: null
     source:
       Git: https://github.com/pulp-platform/axi_llc
@@ -114,7 +114,7 @@ packages:
       Git: [email protected]:AlSaqr-platform/can_bus.git
     dependencies: []
   cheshire:
-    revision: ad8513e13ea62e4999fafcea49d9222d0975de9f
+    revision: 74756f851447e3ad1643299baa17220e1365b400
     version: null
     source:
       Git: https://github.com/pulp-platform/cheshire.git
@@ -193,7 +193,7 @@ packages:
     - fpnew
     - tech_cells_generic
   cva6:
-    revision: 6c6265e9e94494eac446f56c999e8c5dce63fbe8
+    revision: 6503a4c88ff2e274724cbebce8d25fb883d8b8a8
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
@@ -417,7 +417,7 @@ packages:
     - hwpe-stream
     - tech_cells_generic
   redundancy_cells:
-    revision: 09cd9514d52145530fa432e6692ed33aec6c04b6
+    revision: 3fbd080e479f194f68e51dbe262e62c4362868bd
     version: null
     source:
       Git: https://github.com/pulp-platform/redundancy_cells.git
@@ -427,8 +427,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
-    version: 0.4.2
+    revision: e4b20be8833180863ebc64675c93b1694239c505
+    version: null
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -13,7 +13,7 @@ package:
 dependencies:
   register_interface: { git: https://github.com/pulp-platform/register_interface.git,   version: 0.4.2                                }
   axi:                { git: https://github.com/pulp-platform/axi.git,                  version: 0.39.1                               }
-  cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: ad8513e13ea62e4999fafcea49d9222d0975de9f } # branch: astral
+  cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: 74756f851447e3ad1643299baa17220e1365b400 } # branch: astral
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh
   dyn_mem:            { git: https://github.com/pulp-platform/dyn_spm.git,              rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main
   safety_island:      { git: https://github.com/pulp-platform/safety_island.git,        rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield
@@ -100,7 +100,21 @@ sources:
 
   - target: all(synthesis, not(fpga))
     files:
-      - target/synth/src/carfield_synth_wrap.sv
+      - tech/sourcecode/tc_clk.sv
+      - tech/sourcecode/tc_sram.sv
+      - target/synth/carfield_synth_wrap.sv
+
+  - target: tech_sim
+    files:
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_128x40m2b1w0.v
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x32m2b1w1.v
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x44m2b1w1.v
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x46m2b1w1.v
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x64m2b1w1.v
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x128m2b1w1.v
+      - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_1024x64m4b1w1.v
+      - tech/sourcecode/tc_clk.sv
+      - tech/sourcecode/tc_sram.sv
 
   - target: all(xilinx, fpga, xilinx_vanilla)
     files:
@@ -118,6 +132,13 @@ sources:
 
   - target: intel16_elab_only
     files:
+      # - tech/sourcecode/macros/sram_256x32.v
+      # - tech/sourcecode/macros/sram_128x40.v
+      # - tech/sourcecode/macros/sram_256x128.v
+      # - tech/sourcecode/macros/sram_256x44.v
+      # - tech/sourcecode/macros/sram_256x46.v
+      # - tech/sourcecode/tc_clk.sv
+      # - tech/sourcecode/tc_sram.sv
       - nonfree/intel16/sourcecode/tc_clk.sv
       - nonfree/intel16/sourcecode/tc_sram.sv
       - nonfree/intel16/sourcecode/configurable_delay.sv

diff --git a/README.md b/README.md
@@ -58,6 +58,10 @@ make help
 
 The Make files are autodocumented.
 
+### Technology
+
+It is possible to initialize an available technology design flow by running `make tech-init` after cloning the repo.
+
 ## License
 
 Unless specified otherwise in the respective file headers, all code checked into this repository is

diff --git a/bender-sim.mk b/bender-sim.mk
@@ -9,3 +9,8 @@
 sim_targs += -t sim
 sim_targs += -t test
 sim_targs += -t simulation
+ifeq ($(TECH_SIM), 1)
+	sim_targs += -t tech_sim
+	sim_defs  += -D INITIALIZE_MEMORY
+	sim_defs  += -D INITIALIZE_OUTPUT
+endif
diff --git a/carfield.mk b/carfield.mk
@@ -26,6 +26,8 @@ CAR_SIM_DIR := $(CAR_TGT_DIR)/sim
 # Questasim
 CAR_VSIM_DIR := $(CAR_TGT_DIR)/sim/vsim
 
+TECH_ROOT   := $(CAR_ROOT)/tech
+
 BENDER      ?= bender
 BENDER_ROOT ?= $(CAR_ROOT)/.bender
 BENDER_PATH ?= $(shell which $(BENDER))
@@ -357,6 +359,14 @@ car-check-litmus-tests: $(LITMUS_WORK_DIR)/litmus.log
 	grep "Warning positive differences" $(LITMUS_WORK_DIR)/compare.log
 	! grep "Warning negative differences" $(LITMUS_WORK_DIR)/compare.log
 
+##############
+# Technology #
+##############
+tech-repo := [email protected]:Astral/gf12.git
+tech-init:
+	git clone $(tech-repo) tech
+	$(MAKE) -C $(TECH_ROOT) init
+
 ########
 # Help #
 ########

diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv
@@ -549,6 +549,7 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
   AxiUserErrLsb     : 4,
   RegMaxReadTxns    : 8,
   RegMaxWriteTxns   : 8,
+  AxiToRegCut       : 1,
   RegAmoNumCuts     : 1,
   RegAmoPostCut     : 1,
   // External AXI ports (at most 8 ports and rules)

diff --git a/sw/tests/bare-metal/pulpd/sw.mk b/sw/tests/bare-metal/pulpd/sw.mk
@@ -26,6 +26,7 @@ PULPD_BUILD_TARGETS := $(addsuffix /build,$(PULPD_TEST_DIRS))
 $(PULPD_SW_DIR)/%/build: $(PULPD_ROOT) | venv
 	# Compile
 	$(MAKE) -C $(PULPD_SW_DIR)/$* all
+	$(MAKE) -C $(PULPD_SW_DIR)/$* dis > $(CAR_PULPD_SW)/$*.dump
 	cp $@/test/test $(CAR_PULPD_SW)/$*.elf
 	$(PULPD_RISCV)-objcopy $(remove_sections) $(CAR_PULPD_SW)/$*.elf
 	cp $(CAR_PULPD_SW)/$*.elf $@/test/test.elf

diff --git a/target/sim/sim.mk b/target/sim/sim.mk
@@ -42,6 +42,10 @@ RUNTIME_DEFINES += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\"
 ## @section Questasim simulator target
 
 QUESTA_FLAGS := -permissive -suppress 3009 -suppress 8386 -error 7 +UVM_NO_RELNOTES
+ifeq ($(TECH_SIM), 1)
+	QUESTA_FLAGS += +nospecify
+	QUESTA_FLAGS += -suppress 13271
+endif
 ifdef DEBUG
 	VOPT_FLAGS := $(QUESTA_FLAGS) +acc
 	VSIM_FLAGS := $(QUESTA_FLAGS)
@@ -54,7 +58,7 @@ endif
 
 .PHONY: $(CAR_VSIM_DIR)/compile.carfield_soc.tcl
 $(CAR_VSIM_DIR)/compile.carfield_soc.tcl:
-	$(BENDER) script vsim $(common_targs) $(sim_targs) $(common_defs) $(safed_defs) --vlog-arg="$(RUNTIME_DEFINES)" --compilation-mode separate > $@
+	$(BENDER) script vsim $(common_targs) $(sim_targs) $(sim_defs) $(common_defs) $(safed_defs) --vlog-arg="$(RUNTIME_DEFINES)" --compilation-mode separate > $@
 	echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
 	echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@