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Add FLL lock memory mapped register and small fixes for post-synthesis simulations #696

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Add FLL lock memory mapped register and small fixes for post-synthesis simulations

Add FLL lock memory mapped register and small fixes for post-synthesis simulations #696

Triggered via pull request September 5, 2024 21:07
@LuigiGhiondaLuigiGhionda
opened #56
lg/pss_sim
Status Failure
Total duration 6h 0m 21s
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The job running on runner GitHub Actions 7 has exceeded the maximum execution time of 360 minutes.