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Add VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm #619

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Sep 30, 2020
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Add VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm #619

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d003e40
New section in vqfn.yaml for VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm
justyn Sep 10, 2020
e0031bc
Adjustments to VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm
justyn Sep 26, 2020
eed83aa
Fix EP_size_y tolerance, minimum was incorrectly specified.
justyn Sep 26, 2020
35aed9b
Improve format of body_size_{x,y} to be more succint.
justyn Sep 26, 2020
6329435
Use default grid setting for VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm
justyn Sep 30, 2020
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44 changes: 44 additions & 0 deletions scripts/Packages/Package_NoLead__DFN_QFN_LGA_SON/size_definitions/qfn/vqfn.yaml
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Expand Up @@ -561,6 +561,50 @@ VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm:
#suffix: '_Pad{pad_x:.2f}x{pad_y:.2f}mm_HandSolder'
#include_suffix_in_3dpath: 'False'

VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm:
device_type: 'VQFN'
size_source: 'https://www.ti.com/lit/ds/slvs589d/slvs589d.pdf#page=33'
ipc_class: 'qfn'
body_size_x:
minimum: 4.85
nominal: 5
maximum: 5.15
body_size_y:
minimum: 4.85
nominal: 5
maximum: 5.15
overall_height:
minimum: 0.8
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maximum: 1
lead_width:
minimum: 0.18
maximum: 0.3
lead_len:
minimum: 0.3
maximum: 0.5

EP_size_x:
minimum: 2.95
nominal: 3.15
maximum: 3.25
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EP_size_y:
minimum: 2.95
nominal: 3.15
maximum: 3.25
EP_num_paste_pads: [2, 2]

thermal_vias:
count: [3, 3]
drill: 0.2
paste_via_clearance: 0.1
EP_paste_coverage: 0.7
grid: [1.2, 1.2]
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Why did you choose those values?

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@justyn justyn Sep 26, 2020 •
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Sorry I had not updated all the values in this section from VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm.

The grid values I have updated to 1.0, 1.0 to match the datasheet.

I note that paste_via_clearance and EP_paste_coverage have default values in the script, so for now I have removed them from this definition entirely. If that is not correct I would appreciate some guidance on how to select the values.

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Good choice on using defaults for the EP parameters.
I suggest to do the same with the grid.

This footprint is supposed to be build according to IPC spec (it has no Texas_ prefix). With the current values (grid, thermal_vias, EP_num_paste_pads) you are mixing both. Resulting in vias below the paste which will lead to solder loss.
Without the grid-setting, the vias are placed no-overlapping with the paste.

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Thanks for the explanation, I have removed the grid line to allow the defaults, as you say the vias now don't overlap with the paste.

I've added a screenshot of the ThermalVias variant to the top of the PR.

paste_avoid_via: False

pitch: 0.5
num_pins_x: 8
num_pins_y: 8

VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm:
device_type: 'VQFN'
#manufacturer: 'man'
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