Merge pull request #95 from dshadoff/Fix_approximate_MAWR_wait

Approximate effects of MAWR slicing ( #5 , #56 )
pce-devel · Jul 7, 2022 · ca1873a · ca1873a
2 parents 0944f58 + c5e219d
commit ca1873a
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Showing 3 changed files with 72 additions and 0 deletions.
diff --git a/mednafen/src/hw_video/huc6270/vdc.cpp b/mednafen/src/hw_video/huc6270/vdc.cpp
@@ -297,6 +297,14 @@ void VDC::SetLayerEnableMask(uint64 mask)
  userle = mask;
 }
 
+bool VDC::IsActiveDisplay(void)
+{
+ if ((VPhase == VPHASE_VDW) && (HPhase == HPHASE_HDW))
+  return true;
+ else
+  return false;
+}
+
 void VDC::RunSATDMA(int32 cycles, bool force_completion)
 {
  assert(sat_dma_counter > 0);
@@ -1333,6 +1341,18 @@ uint8 VDC::Read(uint32 A, int32 &next_event, bool peek)
 	      pending_read_addr = MARR;
 	      MARR += vram_inc_tab[(CR >> 11) & 0x3];
 
+	      // Simulate MAWR round-robin; implementing it properly would require changing too much code
+	      // Assume a 50% hit rate on missing the CPU window, taking a 1-cycle penalty
+	      // when committing such a word.
+	      if (IsActiveDisplay())
+	      {
+//	       if (MAWRPhase && ((select & 0x1F) == 0x02))
+//	       {
+	        ActiveDisplayPenaltyCycles++;
+//	       }
+//	       MAWRPhase = (MAWRPhase == true) ? false : true;
+	      }
+
 	      CheckAndCommitPending();
              }
             }
@@ -1372,6 +1392,19 @@ uint16 VDC::Read16(bool A, bool peek)
     pending_read_addr = MARR;
     MARR += vram_inc_tab[(CR >> 11) & 0x3];
 
+    // Simulate MAWR round-robin; implementing it properly would require changing too much code
+    // Assume a 50% hit rate on missing the CPU window, taking a 1-cycle penalty
+    // when committing such a word.
+    if (IsActiveDisplay())
+    {
+//     if (MAWRPhase)
+//     {
+      ActiveDisplayPenaltyCycles++;
+      ActiveDisplayPenaltyCycles++;
+//     }
+//     MAWRPhase = (MAWRPhase == true) ? false : true;
+    }
+
     CheckAndCommitPending();
    }
   }
@@ -1462,6 +1495,18 @@ void VDC::Write(uint32 A, uint8 V, int32 &next_event)
 			pending_write_latch = write_latch | (V << 8);
 	                MAWR += vram_inc_tab[(CR >> 11) & 0x3];
 
+			// Simulate MAWR round-robin; implementing it properly would require changing too much code
+			// Assume a 50% hit rate on missing the CPU window, taking a 1-cycle penalty
+			// when committing such a word.
+			if (IsActiveDisplay())
+			{
+//			 if (MAWRPhase && ((select & 0x1F) == 0x03))
+//			 {
+			  ActiveDisplayPenaltyCycles++;
+//			 }
+//			 MAWRPhase = (MAWRPhase == true) ? false : true;
+			}
+
 			CheckAndCommitPending();
                        }
                        break;
@@ -1590,6 +1635,19 @@ void VDC::Write16(bool A, uint16 V)
 			pending_write_latch = V;
 	                MAWR += vram_inc_tab[(CR >> 11) & 0x3];
 
+			// Simulate MAWR round-robin; implementing it properly would require changing too much code
+			// Assume a 50% hit rate on missing the CPU window, taking a 1-cycle penalty
+			// when committing such a word.
+			if (IsActiveDisplay())
+			{
+//			 if (MAWRPhase)
+//			 {
+			  ActiveDisplayPenaltyCycles++;
+			  ActiveDisplayPenaltyCycles++;
+//			 }
+//			 MAWRPhase = (MAWRPhase == true) ? false : true;
+			}
+
 			CheckAndCommitPending();
                        break;
 

diff --git a/mednafen/src/hw_video/huc6270/vdc.h b/mednafen/src/hw_video/huc6270/vdc.h
@@ -272,6 +272,10 @@ class VDC
 	void DoVBIRQTest(void);
 	void HDS_Start(void);
 
+	bool IsActiveDisplay(void);
+	uint32 ActiveDisplayPenaltyCycles = 0;   // to simulate the MAWR time-slot 
+	bool MAWRPhase = false;   // to simulate the MAWR time-slot 
+
 	void StateExtra(LEPacker &sl_packer, bool load);
 	void StateAction(StateMem *sm, const unsigned load, const bool data_only, const char *sname);
 

diff --git a/mednafen/src/pce/vce.cpp b/mednafen/src/pce/vce.cpp
@@ -77,6 +77,16 @@ bool VCE::WS_Hook(int32 vdc_cycles)
   ret = false;
  }
 
+ for(unsigned chip = 0; chip < chip_count; chip++)
+ {
+  while (vdc[chip].ActiveDisplayPenaltyCycles > 0)  // try to make accesses to ActiveDisplayPenaltyCycles as atomic as possible
+  {
+   to_steal++;
+   vdc[chip].ActiveDisplayPenaltyCycles--;
+  }
+ }
+
+
  if(to_steal > 0)
  {
   HuCPU.StealCycles(to_steal);