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StencilStream Version 1.0.0

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@JOOpdenhoevel JOOpdenhoevel released this 03 Dec 11:35
· 612 commits to master since this release

This release contains the isolated StencilStream library as well as synthesized application binaries. All of these binaries have been synthesized using oneAPI version beta-10, and the targeted boards are the Nallatech/Bittware 520N Board as well as the Intel PAC Stratix 10. Below are performance metrics of some sample applications. The conway application is optimized for readability, not for performance, and is therefore not listed.

Nallatech/Bittware 520N Board (Stratix 10 GX 2800)

Application Main Loop II Pipeline Depth Cycle Frequency Generations per Second Overall Performance Logic Usage Register Usage RAM Usage DSP Usage
hotspot 1.05 cycles 225 cores 79.63 MHz 16,328 G/s 256.84 GFLOPS 85.34% 51.23% 38.31% 58.64%
fdtd 1.73 cycles 30 cores 225 MHz 233.10 G/s 29.02 KFLOPS 83.19% 50.37% 43.91% 45.42%

Intel PAC (Stratix 10 SX)

Application Main Loop II Pipeline Depth Cycle Frequency Generations per Second Overall Performance Logic Usage Register Usage RAM Usage DSP Usage
hotspot 1.06 cycles 100 cores 225.00 MHz 20,161.29 G/s 317.17 GFLOPS 64.26% 35.75% 25.09% 26.11%
fdtd 1.45 cycles 20 cores 218.00 MHz 178.95 G/s 24.43 KFLOPS 69.41% 37.87% 34.66% 30.29%