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Merge branch 'add-support-s10mxhbm' into 'master'
Add support Stratix 10 MX with HBM2 See merge request pc2/HPCC_FPGA!10
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19 changes: 19 additions & 0 deletions
19
RandomAccess/settings/settings.gen.intel.random_access_kernels_single.s10mxhbm.py
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global_memory_name = "HBM" | ||
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def generate_attributes(num_replications, num_global_memory_banks=32): | ||
""" | ||
Generates the kernel attributes for the global memory. They specify in which | ||
global memory the buffer is located. The buffers will be placed using a | ||
round robin scheme using the available global memory banks and the number of | ||
replications that should be generated (e.g. if a global memory contains multiple banks) | ||
@param num_replications Number okernel replications | ||
@param num_global_memory_banks Number of global memory banks that should be used for generation | ||
@return Array of strings that contain the attributes for every kernel | ||
""" | ||
global_memory_names = [ "%s%d" % (global_memory_name, i) for i in range(num_global_memory_banks)] | ||
return [ "__attribute__((buffer_location(\"%s\")))" | ||
% (global_memory_names[i % num_global_memory_banks]) | ||
for i in range(num_replications)] |
18 changes: 13 additions & 5 deletions
18
RandomAccess/settings/settings.link.xilinx.random_access_kernels_single.hbm.generator.ini
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@@ -1,8 +1,16 @@ | ||
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# Set number of available SLRs | ||
# PY_CODE_GEN num_slrs = 3 | ||
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[connectivity] | ||
nk=accessMemory_0:{TOTAL_KERNEL_NUMBER} | ||
nk=accessMemory_0:$PY_CODE_GEN num_replications$ | ||
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# slrs | ||
slr=accessMemory_0_{KERNEL_NUMBER}:SLR{KERNEL_NUMBER_DEC} | ||
# Assign kernels to the SLRs | ||
# PY_CODE_GEN block_start [replace(local_variables=locals()) for i in range(num_replications)] | ||
slr=accessMemory_0_$PY_CODE_GEN i+1$:SLR$PY_CODE_GEN i % num_slrs$ | ||
# PY_CODE_GEN block_end | ||
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# matrix ports | ||
sp=accessMemory_0_{KERNEL_NUMBER}.m_axi_gmem:HBM[{KERNEL_NUMBER_DEC}] | ||
# Assign the kernels to the memory ports | ||
# PY_CODE_GEN block_start [replace(local_variables=locals()) for i in range(num_replications)] | ||
sp=accessMemory_0_$PY_CODE_GEN i+1$.m_axi_gmem:HBM[$PY_CODE_GEN i$] | ||
# PY_CODE_GEN block_end |
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#!/bin/bash | ||
# | ||
# Synthesize the STREAM single kernel for the Stratix 10 MX HBM board on Noctua. | ||
# Submit this script to sbatch in this folder! | ||
# | ||
#SBATCH -p fpgasyn | ||
#SBATCH --exclusive | ||
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module load intelFPGA_pro/19.4.0 | ||
module load intel_s10mx/19.3.0 | ||
module load lang/Python/3.7.0-foss-2018b | ||
module load devel/CMake/3.15.3-GCCcore-8.3.0 | ||
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SCRIPT_PATH=${SLURM_SUBMIT_DIR} | ||
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BENCHMARK_DIR=${SCRIPT_PATH}/../ | ||
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BUILD_DIR_4K=${SCRIPT_PATH}/../../build/synth/STREAM-s10xm_hbm-4k | ||
BUILD_DIR_8K=${SCRIPT_PATH}/../../build/synth/STREAM-s10xm_hbm-8k | ||
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mkdir -p ${BUILD_DIR_4K} | ||
cd ${BUILD_DIR_4K} | ||
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cmake ${BENCHMARK_DIR} -DDEVICE_BUFFER_SIZE=4096 -DVECTOR_COUNT=8 -DNUM_REPLICATIONS=32 \ | ||
-DAOC_FLAGS="-fpc -fp-relaxed -global-ring" \ | ||
-DINTEL_CODE_GENERATION_SETTINGS=${BENCHMARK_DIR}/settings/settings.gen.intel.stream_kernels_single.s10mxhbm.py | ||
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make stream_kernels_single_intel& | ||
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mkdir -p ${BUILD_DIR_8K} | ||
cd ${BUILD_DIR_8K} | ||
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cmake ${BENCHMARK_DIR} -DDEVICE_BUFFER_SIZE=8192 -DVECTOR_COUNT=8 -DNUM_REPLICATIONS=32 \ | ||
-DAOC_FLAGS="-fpc -fp-relaxed -global-ring" \ | ||
-DINTEL_CODE_GENERATION_SETTINGS=${BENCHMARK_DIR}/settings/settings.gen.intel.stream_kernels_single.s10mxhbm.py | ||
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make stream_kernels_single_intel& | ||
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wait |
19 changes: 19 additions & 0 deletions
19
STREAM/settings/settings.gen.intel.stream_kernels_single.s10mxhbm.py
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@@ -0,0 +1,19 @@ | ||
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global_memory_name = "HBM" | ||
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def generate_attributes(num_replications, num_global_memory_banks=32): | ||
""" | ||
Generates the kernel attributes for the global memory. They specify in which | ||
global memory the buffer is located. The buffers will be placed using a | ||
round robin scheme using the available global memory banks and the number of | ||
replications that should be generated (e.g. if a global memory contains multiple banks) | ||
@param num_replications Number okernel replications | ||
@param num_global_memory_banks Number of global memory banks that should be used for generation | ||
@return Array of strings that contain the attributes for every kernel | ||
""" | ||
global_memory_names = [ "%s%d" % (global_memory_name, i) for i in range(num_global_memory_banks)] | ||
return [ "__attribute__((buffer_location(\"%s\")))" | ||
% (global_memory_names[i % num_global_memory_banks]) | ||
for i in range(num_replications)] |
36 changes: 22 additions & 14 deletions
36
STREAM/settings/settings.link.xilinx.stream_kernels.hbm.generator.ini
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@@ -1,17 +1,25 @@ | ||
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# Set number of available SLRs | ||
# PY_CODE_GEN num_slrs = 3 | ||
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[connectivity] | ||
nk=copy_0:{TOTAL_KERNEL_NUMBER} | ||
nk=scale_0:{TOTAL_KERNEL_NUMBER} | ||
nk=add_0:{TOTAL_KERNEL_NUMBER} | ||
nk=triad_0:{TOTAL_KERNEL_NUMBER} | ||
nk=copy_0:$PY_CODE_GEN num_replications$ | ||
nk=scale_0:$PY_CODE_GEN num_replications$ | ||
nk=add_0:$PY_CODE_GEN num_replications$ | ||
nk=triad_0:$PY_CODE_GEN num_replications$ | ||
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# slrs | ||
slr=copy_0_{KERNEL_NUMBER}:SLR{KERNEL_NUMBER_DEC} | ||
slr=scale_0_{KERNEL_NUMBER}:SLR{KERNEL_NUMBER_DEC} | ||
slr=add_0_{KERNEL_NUMBER}:SLR{KERNEL_NUMBER_DEC} | ||
slr=triad_0_{KERNEL_NUMBER}:SLR{KERNEL_NUMBER_DEC} | ||
# Assign kernels to the SLRs | ||
# PY_CODE_GEN block_start [replace(local_variables=locals()) for i in range(num_replications)] | ||
slr=copy_0_$PY_CODE_GEN i+1$:SLR$PY_CODE_GEN i % num_slrs$ | ||
slr=scale_0_$PY_CODE_GEN i+1$:SLR$PY_CODE_GEN i % num_slrs$ | ||
slr=add_0_$PY_CODE_GEN i+1$:SLR$PY_CODE_GEN i % num_slrs$ | ||
slr=triad_0_$PY_CODE_GEN i+1$:SLR$PY_CODE_GEN i % num_slrs$ | ||
# PY_CODE_GEN block_end | ||
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# matrix ports | ||
sp=copy_0_{KERNEL_NUMBER}.m_axi_gmem:HBM[0:2] | ||
sp=scale_0_{KERNEL_NUMBER}.m_axi_gmem:HBM[0:2] | ||
sp=add_0_{KERNEL_NUMBER}.m_axi_gmem:HBM[0:2] | ||
sp=triad_0_{KERNEL_NUMBER}.m_axi_gmem:HBM[0:2] | ||
# Assign the kernels to the memory ports | ||
# PY_CODE_GEN block_start [replace(local_variables=locals()) for i in range(num_replications)] | ||
sp=copy_0_$PY_CODE_GEN i+1$.m_axi_gmem:HBM[$PY_CODE_GEN 2*i$:$PY_CODE_GEN 2*i+1$] | ||
sp=scale_0_$PY_CODE_GEN i+1$.m_axi_gmem:HBM[$PY_CODE_GEN 2*i$:$PY_CODE_GEN 2*i+1$] | ||
sp=add_0_$PY_CODE_GEN i+1$.m_axi_gmem:HBM[$PY_CODE_GEN 2*i$:$PY_CODE_GEN 2*i+1$] | ||
sp=triad_0_$PY_CODE_GEN i+1$.m_axi_gmem:HBM[$PY_CODE_GEN 2*i$:$PY_CODE_GEN 2*i+1$] | ||
# PY_CODE_GEN block_end |
19 changes: 14 additions & 5 deletions
19
STREAM/settings/settings.link.xilinx.stream_kernels_single.hbm.generator.ini
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Original file line number | Diff line number | Diff line change |
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@@ -1,8 +1,17 @@ | ||
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# Set number of available SLRs | ||
# PY_CODE_GEN num_slrs = 3 | ||
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[connectivity] | ||
nk=calc_0:{TOTAL_KERNEL_NUMBER} | ||
nk=calc_0:$PY_CODE_GEN num_replications$ | ||
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# slrs | ||
slr=calc_0_{KERNEL_NUMBER}:SLR{KERNEL_NUMBER_DEC} | ||
# Assign kernels to the SLRs | ||
# PY_CODE_GEN block_start [replace(local_variables=locals()) for i in range(num_replications)] | ||
slr=calc_0_$PY_CODE_GEN i+1$:SLR$PY_CODE_GEN i % num_slrs$ | ||
# PY_CODE_GEN block_end | ||
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# matrix ports | ||
sp=calc_0_{KERNEL_NUMBER}.m_axi_gmem:HBM[{KERNEL_NUMBER_DEC}] | ||
# Assign the kernels to the memory ports | ||
# PY_CODE_GEN block_start [replace(local_variables=locals()) for i in range(num_replications)] | ||
sp=calc_0_$PY_CODE_GEN i+1$.m_axi_gmem:HBM[$PY_CODE_GEN i$] | ||
# PY_CODE_GEN block_end |
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