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[Gen 4] Optimize QSPI flash writes and erasures #2841

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[Gen 4] Optimize QSPI flash writes and erasures #2841

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f909842
[rtl872x] flash: use 4IO or 2IO modes for writes and write up to 256 …
avtolstoy Nov 12, 2024
721b552
[third_party] ambd_sdk: a6b17b249f9134ae5fe001d884558c88bf78a872 cali…
avtolstoy Nov 12, 2024
b9cabeb
minor
avtolstoy Nov 12, 2024
e80ed62
[rtl872x] flash: fix page boundary/alignment issue
avtolstoy Nov 12, 2024
2aea3f9
[rtl872x] get RAM from MBR, fix GD25 4PP
avtolstoy Nov 19, 2024
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4 changes: 2 additions & 2 deletions build/arm/linker/rtl872x/platform_ram_m23.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ x
| KM0 part1 static RAM | | |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | Heap |
| KM0 part1 RAM code | | |
+-----------------------------+ 0x00086000 | |
+-----------------------------+ 0x00083400 | |
| | | |
| KM0 MBR static RAM | | |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
Expand Down Expand Up @@ -78,7 +78,7 @@ platform_km0_bootloader_stack_start = platform_km0_bootloader_stack_end - platfo


/* Bootloader RAM, contains static data and code */
platform_km0_mbr_ram_size = 16K;
platform_km0_mbr_ram_size = 5K;
platform_km0_mbr_ram_start = platform_km0_ram_start;
platform_km0_mbr_ram_end = platform_km0_mbr_ram_start + platform_km0_mbr_ram_size;

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34 changes: 1 addition & 33 deletions hal/src/rtl872x/core_hal.c
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Original file line number Diff line number Diff line change
Expand Up @@ -264,39 +264,7 @@ void HAL_Core_Restore_Interrupt(IRQn_Type irqn) {

#if HAL_PLATFORM_PROHIBIT_XIP
static void prohibit_xip(void) {
const uint8_t regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos;
// Disable MPU
MPU->CTRL = 0;
// Clear all regions
for (uint8_t i = 0; i < regions; i++) {
MPU->RNR = i;
MPU->RASR = 0;
MPU->RBAR = 0;
}

uint8_t st = 0;
sd_nvic_critical_region_enter(&st);

// Forbid access to XIP
MPU->RNR = 0;
MPU->RBAR = EXTERNAL_FLASH_XIP_BASE;
// XN: 1, instruction fetches disabled
// AP: 0b000, all accesses generate a permission fault
// TEX: 0b000, S: 0, C: 1, B: 0, as suggested by core manual for flash memory
const uint32_t attr = 0x10050000;
MPU->RASR = attr | (1 << MPU_RASR_ENABLE_Pos) | ((31 - __CLZ(EXTERNAL_FLASH_XIP_LENGTH) - 1) << MPU_RASR_SIZE_Pos);
// Enable MPU
MPU->CTRL = 0x00000005;

sd_nvic_critical_region_exit(st);

// Use a DSB followed by an ISB instruction to ensure that the new MPU configuration is used by subsequent instructions.
__DSB();
__ISB();

// Uncomment the code bellow will trigger hardfault
// uint8_t data = *((uint8_t*)(EXTERNAL_FLASH_XIP_BASE + EXTERNAL_FLASH_OTA_ADDRESS));
// LOG(ERROR, "%d", data);
// FIXME
}
#endif // HAL_PLATFORM_PROHIBIT_XIP

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