Adds the transaction and physical layers of an I2C controller #253
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This is some early work on the lower layers of an I2C controller block. I'm looking to get this reviewed and integrated a bit prematurely since Nathanael is looking at building out an I2C target block and we'd like to avoid stepping on one another's toes. Given all of this has not been integrated into a design yet and is simulation only, everything is up for grabs if we'd like to make changes. I've begun work on an
i2c_core.vhd
(should probably be renamedi2c_controller_top.vhd
or something) that is going to attempt to link up a register control interface to the low-level blocks. It would present read/write data buffers as a streaming interface that we could hook up to FIFOs/RAMs/etc as we see fit.