espi ruby integration

hdl/ip/vhd/espi/BUCK

@@ -8,6 +8,13 @@ rdl_file(
     visibility = ['PUBLIC']
 )
 
+rdl_file(
+    name = "vwire_regs_pkg",
+    src = "vwire_channel/vwire_regs.rdl",
+    outputs = ["vwire_regs_pkg.vhd", "vwire_regs.html"],
+    visibility = ['PUBLIC']
+)
+
 rdl_file(
     name = "espi_regs_pkg",
     src = "sys_regs/espi_regs.rdl",
@@ -23,10 +30,12 @@ vhdl_unit(
         "flash_channel/*.vhd",
         "sys_regs/*.vhd",
         "uart_channel/*.vhd",
+        "vwire_channel/*.vhd",
         "*.vhd"]),
     deps = [
         ":espi_spec_regs_pkg",
         ":espi_regs_pkg",
+        ":vwire_regs_pkg",
         "//hdl/ip/vhd/crc:crc8atm_8wide",
         "//hdl/ip/vhd/fifos:dcfifo_xpm",
         "//hdl/ip/vhd/fifos:dcfifo_mixed_xpm",

hdl/ip/vhd/espi/espi_spec_regs.rdl

@@ -70,7 +70,7 @@ addrmap eSPI_Spec {
             desc = "I/O Mode Support";
             sw = r;
             encode = io_mode_support;
-        } io_mode_support[25:24] = io_mode_support::Any;
+        } io_mode_support[25:24] = io_mode_support::Single;
         field {
             desc = "Open Drain Alert# Select";
             sw = rw;
@@ -88,7 +88,7 @@ addrmap eSPI_Spec {
             desc = "Operating Frequency Support";
             sw = r;
             encode = op_freq;
-        } op_freq_support[18:16] = op_freq::SixtySix;
+        } op_freq_support[18:16] = op_freq::Twenty;
         field {
             desc = "Maximum Wait State allowed";
             sw = rw;
@@ -112,7 +112,7 @@ addrmap eSPI_Spec {
     } general_capabilities;
 
     reg {
-        name = "Maximum Read Request Size";
+        name = "Channel 0 Capabilities";
         default sw = rw;
 
         field {
@@ -156,6 +156,29 @@ addrmap eSPI_Spec {
 
     } ch0_capabilities @0x10;
 
+     reg {
+        name = "Channel 1 Capabilities";
+        default sw = rw;
+
+        field {
+            desc = "";
+        } wire_count_sel[21:16] =  0x0;
+
+        field {
+            desc = "Maximum Virtual Wire Count Supported";
+        } wire_max_supported[13:8] =  0x7;
+
+        field {
+            desc = "Channel Ready";
+            sw = r;
+        } chan_rdy[1:1] =  0x0;
+
+        field {
+            desc = "Channel Enable";
+        } chan_en[0:0] =  0x1;
+
+    } ch1_capabilities @0x20;
+
     reg {
         name = "Channel 2(OOB) Capabilities";
         default sw = rw;

hdl/ip/vhd/espi/espi_spec_regs.vhd

@@ -34,6 +34,7 @@ architecture rtl of espi_spec_regs is
     signal device_id        : device_id_type;
     signal gen_capabilities : general_capabilities_type;
     signal ch0_capabilities : ch0_capabilities_type;
+    signal ch1_capabilities : ch1_capabilities_type;
     signal ch3_capabilities : ch3_capabilities_type;
     signal readdata_valid   : std_logic;
     signal readdata         : std_logic_vector(31 downto 0);
@@ -52,6 +53,7 @@ begin
             device_id <= rec_reset;
             gen_capabilities <= rec_reset;
             ch0_capabilities <= rec_reset;
+            ch1_capabilities <= rec_reset;
             ch3_capabilities <= rec_reset;
         elsif rising_edge(clk) then
             if regs_if.addr = GENERAL_CAPABILITIES_OFFSET and regs_if.write = '1' then
@@ -73,6 +75,15 @@ begin
                 ch0_capabilities.chan_rdy <= ch0_capabilities.chan_rdy;
             end if;
 
+            if regs_if.addr = CH1_CAPABILITIES_OFFSET and regs_if.write = '1' then
+                ch1_capabilities <= unpack(regs_if.wdata);
+                -- clean up RO fields by keeping current val
+                ch1_capabilities.wire_max_supported <= ch1_capabilities.wire_max_supported;
+                ch1_capabilities.chan_rdy <= ch1_capabilities.chan_rdy;
+            else
+                ch1_capabilities.chan_rdy <= ch1_capabilities.chan_en;
+            end if;
+
             if regs_if.addr = CH3_CAPABILITIES_OFFSET and regs_if.write = '1' then
                 ch3_capabilities <= unpack(regs_if.wdata);
                 -- clean up RO fields by keeping current val
@@ -105,6 +116,10 @@ begin
                     readdata <= pack(gen_capabilities);
                 when CH0_CAPABILITIES_OFFSET =>
                     readdata <= pack(ch0_capabilities);
+                when CH1_CAPABILITIES_OFFSET =>
+                    readdata <= pack(ch1_capabilities);
+                when CH3_CAPABILITIES_OFFSET =>
+                    readdata <= pack(ch3_capabilities);
                 when others =>
                     readdata <= (others => '0');
             end case;

hdl/ip/vhd/espi/espi_target_top.vhd

@@ -19,6 +19,8 @@ entity espi_target_top is
     port (
         clk   : in    std_logic;
         reset : in    std_logic;
+        axi_clk : in std_logic;
+        axi_reset : in std_logic;
         -- Axilite interface
         axi_if : view axil_target;
         -- phy interface
@@ -68,16 +70,43 @@ architecture rtl of espi_target_top is
     signal host_to_sp_espi : st_uart_t;
     signal sp_to_host_espi : uart_resp_t;
     signal aborted_due_to_bad_crc : boolean;
+    signal cs_n_syncd : std_logic;
+    signal sclk_syncd : std_logic;
+    signal vwire_if : vwire_if_type;
+    signal vwire_avail : std_logic;
 
 begin
 
+    -- sync
+    cs_meta_sync_inst: entity work.meta_sync
+     generic map(
+        stages => 1
+    )
+     port map(
+        async_input => cs_n,
+        clk => clk,
+        sycnd_output => cs_n_syncd
+    );
+
+    sclk_meta_sync_inst: entity work.meta_sync
+     generic map(
+        stages => 1
+    )
+     port map(
+        async_input => sclk,
+        clk => clk,
+        sycnd_output => sclk_syncd
+    );
+
     -- link layer
     link_layer_top_inst: entity work.link_layer_top
      port map(
         clk => clk,
         reset => reset,
-        cs_n => cs_n,
-        sclk => sclk,
+        axi_clk => axi_clk,
+        axi_reset => axi_reset,
+        cs_n => cs_n_syncd,
+        sclk => sclk_syncd,
         io => io,
         io_o => io_o,
         io_oe => io_oe,
@@ -95,8 +124,8 @@ begin
     -- system (axi-lite) register block
    espi_sys_regs_inst: entity work.espi_regs
     port map(
-       clk => clk,
-       reset => reset,
+       clk => axi_clk,
+       reset => axi_reset,
        axi_if => axi_if,
        dbg_chan => dbg_chan
    );
@@ -108,6 +137,7 @@ begin
             reset           => reset,
             is_crc_byte     => is_crc_byte,
             regs_if         => regs_if,
+            vwire_if        => vwire_if,
             chip_sel_active => chip_sel_active,
             data_to_host    => data_to_host,
             data_from_host  => data_from_host,
@@ -124,7 +154,8 @@ begin
             pc_free => pc_free,
             pc_avail => pc_avail,
             np_free => np_free,
-            np_avail => np_avail
+            np_avail => np_avail,
+            vwire_avail => vwire_avail
         );
 
     -- espi-internal register block
@@ -173,4 +204,13 @@ begin
        np_avail => np_avail
    );
 
+   -- vwire channel logic
+    vwire_block_inst: entity work.vwire_block
+     port map(
+        clk => clk,
+        reset => reset,
+        espi_reset_flag => '0',
+        wire_tx_avail => vwire_avail,
+        vwire_if => vwire_if
+    );
 end rtl;

hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd

@@ -21,6 +21,8 @@ entity dbg_link_faker is
     port (
         clk   : in    std_logic;
         reset : in    std_logic;
+        axi_clk : in std_logic;
+        axi_reset : in std_logic;
         -- Asserted by command processor during the
         -- transmission of the last command byte (the CRC)
         response_done : in boolean;
@@ -72,15 +74,48 @@ architecture rtl of dbg_link_faker is
     signal cmd_fifo_wusedwds: std_logic_vector(log2ceil(1024) downto 0);
     signal rusedwds: std_logic_vector(log2ceil(1024) downto 0);
     signal resp_fifo_rusedwds: std_logic_vector(log2ceil(1024) downto 0);
+    signal busy: std_logic;
+    signal busy_axi_sync: std_logic;
+    signal alert_pending : std_logic;
+    signal alert_pending_axi_sync : std_logic;
 
 begin
 
-    dbg_chan.busy <= '1' when r.state /= idle else '0';
+    sync_regs: process(clk, reset)
+    begin
+        if reset = '1' then
+            busy <= '0';
+            alert_pending <= '0';
+        elsif rising_edge(clk) then
+            busy <= '1' when r.state /= idle else '0';
+            alert_pending <= '1' when alert_needed else '0';
+        end if;
+    end process;
+
+    busy_meta_sync_inst: entity work.meta_sync
+     generic map(
+        stages => 2
+    )
+     port map(
+        async_input => busy,
+        clk => clk,
+        sycnd_output => busy_axi_sync
+    );
+    alert_meta_sync_inst: entity work.meta_sync
+    generic map(
+       stages => 2
+   )
+    port map(
+       async_input => alert_pending,
+       clk => clk,
+       sycnd_output => alert_pending_axi_sync
+   );
+    dbg_chan.busy <= busy_axi_sync;
     dbg_chan.wstatus.usedwds <= resize(cmd_fifo_wusedwds, dbg_chan.wstatus.usedwds'length);
     dbg_chan.rdstatus.usedwds <= resize(resp_fifo_rusedwds, dbg_chan.rdstatus.usedwds'length);
     dbg_chan.rd.data <= resp_fifo_read_data;
     cs_active <= r.cs_asserted;
-    dbg_chan.alert_pending <= '1' when alert_needed else '0';
+    dbg_chan.alert_pending <= alert_pending_axi_sync;
 
     -- Timer: the fastest byte transfer that can be done is 2 clocks at 66MHz (in quad mode) so we'll
     -- generate a strobe at that speed when enabled to provide effective rate-limiting to the design.
@@ -113,8 +148,8 @@ begin
         showahead_mode => true
     )
      port map(
-        wclk => clk,
-        reset => reset,
+        wclk => axi_clk,
+        reset => axi_reset,
         write_en => dbg_chan.wr.write,
         wdata => dbg_chan.wr.data,
         wfull => open,
@@ -133,7 +168,7 @@ begin
         showahead_mode => true
     )
      port map(
-        wclk => clk,
+        wclk => axi_clk,
         reset => reset,
         write_en => dbg_chan.size.write,
         wdata => dbg_chan.size.data,
@@ -252,7 +287,7 @@ begin
         wdata => data_to_host.data,
         wfull => open,
         wusedwds => open,
-        rclk => clk,
+        rclk => axi_clk,
         rdata => resp_fifo_read_data,
         rdreq => resp_fifo_read_ack,
         rempty => resp_fifo_empty,

hdl/ip/vhd/espi/link_layer/link_layer_top.vhd

@@ -14,6 +14,8 @@ entity link_layer_top is
     port (
         clk   : in    std_logic;
         reset : in    std_logic;
+        axi_clk : in std_logic;
+        axi_reset : in std_logic;
 
         cs_n  : in    std_logic;
         sclk  : in    std_logic;
@@ -46,11 +48,21 @@ architecture rtl of link_layer_top is
     signal dbg_data_to_host : data_channel;
     signal dbg_data_from_host : data_channel;
     signal dbg_alert_needed : boolean;
-    alias  debug_active is dbg_chan.enabled;
+    signal debug_active : boolean;
     signal dbg_chip_sel_active : boolean;
 
 begin
 
+    -- sync from axi domain into the system domain
+    sync_process: process(clk, reset)
+    begin
+        if reset then
+            debug_active <= false;
+    elsif rising_edge(clk) then
+            debug_active <= dbg_chan.enabled;
+        end if;
+    end process;
+
     -- The "real" link layer
     qspi_link_layer: entity work.qspi_link_layer
         port map (
@@ -73,6 +85,8 @@ begin
         port map (
             clk => clk,
             reset => reset,
+            axi_clk => axi_clk,
+            axi_reset => axi_reset,
             response_done => response_done,
             aborted_due_to_bad_crc => aborted_due_to_bad_crc,
             cs_active => dbg_chip_sel_active,

hdl/ip/vhd/espi/link_layer/qspi_link_layer.vhd

@@ -42,6 +42,13 @@ entity qspi_link_layer is
         -- "Streaming" bytes after receipt and deserialization
         data_from_host     : view st_source;
     );
+    attribute mark_debug : string;
+    attribute mark_debug of io_oe        : signal is "TRUE";
+    attribute mark_debug of io_o        : signal is "TRUE";
+    attribute mark_debug of io        : signal is "TRUE";
+    attribute mark_debug of sclk        : signal is "TRUE";
+    attribute mark_debug of cs_n        : signal is "TRUE";
+
 end entity;
 
 architecture rtl of qspi_link_layer is
@@ -56,6 +63,8 @@ architecture rtl of qspi_link_layer is
     -- for a sentinel value
     signal tx_reg            : std_logic_vector(8 downto 0);
     signal rx_reg            : std_logic_vector(8 downto 0);
+    attribute mark_debug of tx_reg        : signal is "TRUE";
+    attribute mark_debug of rx_reg        : signal is "TRUE";
     signal in_turnaround     : boolean;
     signal ta_cnts    : integer range 0 to 2 := 0;
     signal response_phase    : boolean;
@@ -67,6 +76,7 @@ architecture rtl of qspi_link_layer is
     signal cs_cntr : natural range 0 to 3 := 0;
     constant cs_deassert_delay : natural := 2;
 
+
 begin
 
     -- We have some fairly slow minimum delay timings for the alert pin