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// Copyright 2024 Oxide Computer Company | ||
// This is a SystemRDL description of the SW-accessible registers for the I2C core. | ||
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addrmap i2c_core_regs { | ||
name = "I2C core registers"; | ||
desc = "Registers accessible on the AXI bus for interacting with the I2C core."; | ||
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default regwidth = 32; | ||
default sw = rw; | ||
default hw = r; | ||
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reg { | ||
name = "Receive data"; | ||
default sw = r; | ||
default hw = rw; | ||
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field { | ||
desc = "Last 4 bytes recieved"; | ||
} DATA[31:0] = 0; | ||
} RXD; | ||
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reg { | ||
name = "Transmit data"; | ||
default sw = r; | ||
default hw = rw; | ||
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field { | ||
desc = "Next 4 bytes to send"; | ||
} DATA[31:0] = 0; | ||
} TXD; | ||
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reg { | ||
name = "Control bits for I2C communication."; | ||
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field { | ||
desc = "Number of bytes to read/write in the I2C transaction. up to 128 bytes."; | ||
} COUNT[22:16] = 1; | ||
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field { | ||
desc = "I2C Address of target"; | ||
} ADDR[14:8] = 0; | ||
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field { | ||
desc = "2'b00 to read, 2'b01 to write, 2'b10 to random-read."; | ||
} OP[2:1] = 0; | ||
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field { | ||
desc = "'1' to start next transaction."; | ||
} START[0:0] = 0; | ||
} CONTROL; | ||
}; |
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-- This Source Code Form is subject to the terms of the Mozilla Public | ||
-- License, v. 2.0. If a copy of the MPL was not distributed with this | ||
-- file, You can obtain one at https://mozilla.org/MPL/2.0/. | ||
-- | ||
-- Copyright 2024 Oxide Computer Company | ||
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-- AXI-accessible registers for the I2C block | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
use ieee.numeric_std_unsigned.all; | ||
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use work.axil8x32_pkg.all; | ||
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use work.i2c_core_regs_pkg.all; | ||
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entity i2c_core_regs is | ||
port ( | ||
clk : in std_logic; | ||
reset : in std_logic; | ||
axi_if : view axil_target; | ||
); | ||
end entity; | ||
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architecture rtl of i2c_core_regs is | ||
constant AXI_OKAY : std_logic_vector(1 downto 0) := "00"; | ||
signal axi_read_ready_int : std_logic; | ||
signal axi_awready : std_logic; | ||
signal axi_wready : std_logic; | ||
signal axi_bvalid : std_logic; | ||
signal axi_bready : std_logic; | ||
signal axi_arready : std_logic; | ||
signal axi_rvalid : std_logic; | ||
signal axi_rdata : std_logic_vector(31 downto 0); | ||
begin | ||
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-- AXI wiring | ||
axi_if.write_response.resp <= AXI_OKAY; | ||
axi_if.write_response.valid <= axi_bvalid; | ||
axi_if.read_data.resp <= AXI_OKAY; | ||
axi_if.write_data.ready <= axi_wready; | ||
axi_if.write_address.ready <= axi_awready; | ||
axi_if.read_address.ready <= axi_arready; | ||
axi_if.read_data.data <= axi_rdata; | ||
axi_if.read_data.valid <= axi_rvalid; | ||
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axi_bready <= axi_if.write_response.ready; | ||
axi_wready <= awready; | ||
axi_arready <= not rvalid; | ||
axi_read_ready_int <= axi_if.read_address.valid and axi_arready; | ||
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axi: process(clk, reset) | ||
begin | ||
if reset then | ||
axi_awready <= '0'; | ||
axi_bvalid <= '0'; | ||
axi_rvalid <= '0'; | ||
elsif rising_edge(clk) then | ||
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-- bvalid is set on every write and then cleared after bv | ||
if axi_awready then | ||
axi_bvalid <= '1'; | ||
elsif axi_bready then | ||
axi_bvalid <= '0'; | ||
end if; | ||
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end if; | ||
end process; | ||
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end architecture; |
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