Add an enable to Strobe, misc other updates

hdl/ip/vhd/common/BUCK

@@ -27,6 +27,14 @@ vhdl_unit(
     visibility = ['PUBLIC']
 )
 
+vhdl_unit(
+    name = "tristate_if_pkg",
+    srcs = glob(["interfaces/tristate_if_pkg.vhd"]),
+    deps = [],
+    standard = "2019",
+    visibility = ['PUBLIC']
+)
+
 # Strobe
 
 vhdl_unit(

hdl/ip/vhd/common/interfaces/streaming_if_pkg.vhd

@@ -20,12 +20,12 @@ package streaming_if_pkg is
         ready   : std_logic;
     end record;
 
-    view st_source of data_channel is
+    view st_source_if of data_channel is
         valid, data : out;
         ready       : in;
     end view;
 
-    alias st_sink is st_source'converse;
+    alias st_sink_if is st_source_if'converse;
 
 end package;
 

hdl/ip/vhd/common/interfaces/tristate_if_pkg.vhd

@@ -0,0 +1,25 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+-- This package relies on the VHDL 2019 feature for "interfaces"
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package tristate_if_pkg is
+
+    type tristate is record
+        i   : std_logic;
+        o   : std_logic;
+        oe  : std_logic;
+    end record;
+
+    view tristate_if of tristate is
+        i       : in;
+        o, oe   : out;
+    end view;
+
+end package;

hdl/ip/vhd/common/strobe/sims/strobe_tb.vhd

@@ -21,16 +21,19 @@ entity strobe_tb is
 end entity;
 
 architecture tb of strobe_tb is
-    constant TB_TICKS : positive := 10;
+    constant CLK_PER    : time := 8 ns;
+    constant TB_TICKS   : positive := 10;
 begin
 
     th: entity work.strobe_th
         generic map (
-            TICKS => TB_TICKS
+            CLK_PER => CLK_PER,
+            TICKS   => TB_TICKS
         );
 
     bench: process
         alias reset is << signal th.reset : std_logic >>;
+        alias enable is << signal th.dut_enable : std_logic >>;
         alias strobe is << signal th.dut_strobe : std_logic >>;
     begin
         -- Always the first thing in the process, set up things for the VUnit test runner
@@ -41,11 +44,18 @@ begin
 
         while test_suite loop
             if run("test_strobe") then
+                enable <= '1';
                 check_equal(strobe, '0', "Strobe should be low after reset");
-                wait for 72 ns; -- CLK_PER_NS * (TB_TICKS - 1) ns
+                wait for CLK_PER * (TB_TICKS - 1);
                 check_equal(strobe, '0', "Strobe should be low after TB_TICKS-1");
-                wait for 8 ns; -- wait one more period, bringing us to TB_TICKs
+                wait for CLK_PER;
                 check_equal(strobe, '1', "Strobe should be high once the TICKS count is reached");
+            elsif run("test_strobe_enable") then
+                wait for CLK_PER * TB_TICKS;
+                check_equal(strobe, '0', "Strobe should be low after TB_TICKS when not enabled");
+                enable <= '1';
+                wait for CLK_PER * TB_TICKS;
+                check_equal(strobe, '1', "Strobe should be high after TICKs when enabled");
             end if;
         end loop;
 

hdl/ip/vhd/common/strobe/sims/strobe_th.vhd

@@ -15,21 +15,21 @@ library vunit_lib;
 
 entity strobe_th is
     generic (
-        TICKS : positive
+        CLK_PER : time;
+        TICKS   : positive
     );
 end entity;
 
 architecture th of strobe_th is
 
     signal clk          : std_logic := '0';
     signal reset        : std_logic := '1';
+    signal dut_enable   : std_logic := '0';
     signal dut_strobe   : std_logic;
 
 begin
 
-    -- set up a fastish clock for the sim env
-    -- and release reset after a bit of time
-    clk   <= not clk after 4 ns;
+    clk   <= not clk after CLK_PER / 2;
     reset <= '0' after 200 ns;
 
     strobe_inst: entity work.strobe
@@ -39,6 +39,7 @@ begin
         port map (
             clk     => clk,
             reset   => reset,
+            enable  => dut_enable,
             strobe  => dut_strobe
         );
 

hdl/ip/vhd/common/strobe/strobe.vhd

@@ -18,6 +18,7 @@ entity strobe is
         clk     : in std_logic;
         reset   : in std_logic;
 
+        enable  : in std_logic;
         strobe  : out std_logic
     );
 end entity strobe;
@@ -27,14 +28,14 @@ architecture rtl of strobe is
 begin
     strobe_gen: process (clk, reset) is
     begin
-        if reset = '1' then
+        if reset then
             strobe_counter  <= 0;
             strobe          <= '0';
         elsif rising_edge(clk) then
             if strobe_counter = TICKS - 1 then
                 strobe          <= '1';
                 strobe_counter  <= 0;
-            else
+            elsif enable then
                 strobe          <= '0';
                 strobe_counter  <= strobe_counter + 1;
             end if;

hdl/ip/vhd/vunit_components/basic_stream/sims/th_basic_stream.vhd

@@ -17,8 +17,8 @@ use work.basic_stream_pkg.all;
 
 entity th_basic_stream is
     generic (
-        source : basic_source_t;
-        sink: basic_sink_t
+        source  : basic_source_t;
+        sink    : basic_sink_t
     );
 end entity;