GHA and colo runner

.github/workflows/vunit.yml

@@ -0,0 +1,18 @@
+name: vunit
+run-name: ${{ github.actor }} is testing out GitHub Actions
+on:
+  [push]
+jobs:
+  Run-sim:
+    runs-on: self-hosted
+    steps:
+        - run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}."
+        - name: Check out repository code
+          uses: actions/checkout@v4
+          with:
+            submodules: 'true'
+        - name: Update pip reqs
+          run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages
+        - name: Run VUnit tests
+          run: buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done
+

.gitignore

@@ -37,5 +37,8 @@ vivado*.log
 # Yep, even ignore Vivado core dump logs!
 *.log 
 
+# VUnit test results
+**/*.xml
+
 # DrawIO cruft
 **/*.svg.bkp

README.md

@@ -96,6 +96,18 @@ but if you want to see a list of all available buck2 targets you can do: `buck2
 To run a simulation, pick one of the testbench targets and `buck2 run <target>` you may do
 `-- <vunit args>` if you need to pass arguments into VUnit.
 
+### running all sims or sim regressions
+We can use the build system to query for vunit simulation testbenches and have built a .bxl
+that does this and gives you the command line options to run each one found:
+
+`buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen`
+
+If you'd like to run a regression run like the build machine does, you can pipe that into split
+and use the shell to execute each line:
+
+`buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done`
+
+
 ## multitool
 multitool is a collection of quality of live utilities built in-tree for regular use, but whose
 function is small enough to not warrant a self-contained project.

hdl/ip/vhd/espi/sims/espi_tb.vhd

@@ -193,6 +193,7 @@ begin
                 -- temp enable periph 0 msg responses
                 write_bus(net, bus_handle, To_StdLogicVector(CONTROL_OFFSET, bus_handle.p_address_length), std_logic_vector'(X"00000011"));
                 -- Send UART data which will then be looped back and rx'd
+                rnd.InitSeed(rnd'instance_name & to_string(now));
                 payload_size := rnd.RandInt(1, 64);
                 my_queue := build_rand_byte_queue(payload_size);
                 dbg_send_uart_data_cmd(net, my_queue);
@@ -202,7 +203,7 @@ begin
                 check(response.crc_ok, "Send UART CMD resp CRC Check failed");
                 dbg_get_response_size(net, gen_int);
                 print("Payload Size: " & integer'image(payload_size) & ", Response size: " & integer'image(gen_int));
-                wait for 10 * payload_size * 250 ns;  -- approx uart time for payload size
+                wait for 10 * payload_size * 300 ns;  -- approx uart time for payload size
                 status_rec := unpack(response.status);
                 if status_rec.pc_avail /= '1' then
                     dbg_wait_for_alert(net);

hdl/ip/vhd/memories/BUCK

@@ -15,6 +15,7 @@ vhdl_unit(
     srcs = glob(["sims/*.vhd"]),
     deps = [
         ":dual_clock_simple_dpr",
+        "//hdl/ip/vhd/fifos:dcfifo_xpm",
         "//hdl/ip/vhd/vunit_components:sim_gpio"
     ],
     visibility = ['PUBLIC'],

hdl/ip/vhd/vunit_components/BUCK

@@ -20,13 +20,6 @@ vhdl_unit(
     visibility = ['PUBLIC'],
 )
 
-vunit_sim(
-    name = "qspi_vc_tb",
-    srcs = glob(["qspi_controller/sims/*.vhd"]),
-    deps = [":qspi_controller_vc"],
-    visibility = ['PUBLIC'],
-)
-
 vhdl_unit(
     name = "basic_stream",
     srcs = glob(["basic_stream/*.vhd"]),

hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd

@@ -104,7 +104,7 @@ package qspi_vc_pkg is
 
     procedure wait_until_start (
         signal net : inout network_t;
-        constant actor : actor_t;
+        constant actor : actor_t
     );
 
 
@@ -144,7 +144,7 @@ package body qspi_vc_pkg is
 
     procedure wait_until_start (
         signal net : inout network_t;
-        constant actor : actor_t;
+        constant actor : actor_t
     ) is
 
             variable request_msg : msg_t := new_msg(ensure_start);

tools/vunit-sims.bxl

@@ -0,0 +1,29 @@
+# This Source Code Form is subject to the terms of the Mozilla Public
+# License, v. 2.0. If a copy of the MPL was not distributed with this
+# file, You can obtain one at https://mozilla.org/MPL/2.0/.
+#
+# Copyright 2024 Oxide Computer Company
+
+# This function queries the build graph and targets that are
+# simulation targets and runs them
+def vunit_sim(ctx):
+    # start with all the buck2 targets from the root
+    target_universe = ctx.target_universe("//...").target_set()
+    # Get the deps
+    targets = ctx.cquery().deps(target_universe)
+    # Filter for vhdl files in the project
+    vhdl_files = ctx.cquery().kind("vhdl.*", targets)
+    sims = ctx.cquery().attrfilter("is_tb", "True", vhdl_files)
+    sims = sorted(sims, key=lambda x: x.attrs_eager().standard.value())
+     # Eagerly analyze targets
+    results = ctx.analysis(sims)
+    for lbl,result in results.items():
+         ctx.output.print("buck2 run " + str(lbl.raw_target()) + " -- --clean -x " + lbl.name + ".xml")
+
+
+vunit_sim_gen = bxl_main(
+    impl = vunit_sim,
+    cli_args = {
+        # cli args that you want to receive from the command line
+    },
+)