feedback from Nathanael

oxidecomputer · Dec 10, 2024 · 21a33f5 · 21a33f5
1 parent 428ebd1
commit 21a33f5
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Showing 4 changed files with 9 additions and 9 deletions.
diff --git a/hdl/ip/vhd/common/BUCK b/hdl/ip/vhd/common/BUCK
@@ -17,7 +17,7 @@ vhdl_unit(
     visibility = ['PUBLIC'],
 )
 
-# Interfaces - Note these packages require VHDL-2019 support
+# Interfaces
 
 vhdl_unit(
     name = "streaming_if_pkg",

diff --git a/hdl/ip/vhd/common/countdown/countdown.vhd b/hdl/ip/vhd/common/countdown/countdown.vhd
@@ -13,7 +13,7 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+use ieee.numeric_std_unsigned.all;
 
 entity countdown is
     generic (
@@ -24,7 +24,7 @@ entity countdown is
         reset   : in std_logic;
 
         -- target value to count down from
-        count   : in unsigned(SIZE - 1 downto 0);
+        count   : in std_logic_vector(SIZE - 1 downto 0);
         -- loads `count` into internal registers
         load    : in std_logic;
         -- decrement internal counter
@@ -38,7 +38,7 @@ entity countdown is
 end entity countdown;
 
 architecture rtl of countdown is
-    signal counter  : unsigned(SIZE - 1 downto 0);
+    signal counter  : std_logic_vector(SIZE - 1 downto 0);
 begin
     counter_gen: process (clk, reset) is
     begin

diff --git a/hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd b/hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd
@@ -33,7 +33,7 @@ begin
 
     bench: process
         alias reset is << signal th.reset : std_logic >>;
-        alias count is << signal th.dut_count : unsigned >>;
+        alias count is << signal th.dut_count : std_logic_vector >>;
         alias load is << signal th.dut_load : std_logic >>;
         alias decr is << signal th.dut_decr : std_logic >>;
         alias clear is << signal th.dut_clear : std_logic >>;
@@ -49,7 +49,7 @@ begin
             if run("test_reset") then
                 check_true(done = '1', "should be done as it not been loaded");
             elsif run("test_clear") then
-                count   <= to_unsigned(3, count'length);
+                count   <= to_std_logic_vector(3, count'length);
                 load    <= '1';
                 clear   <= '1';
                 wait for CLK_PER;
@@ -65,7 +65,7 @@ begin
                 wait for CLK_PER;
                 check_true(done = '1', "should be done after clear");
             elsif run("test_countdown") then
-                count   <= to_unsigned(3, count'length);
+                count   <= to_std_logic_vector(3, count'length);
                 load    <= '1';
                 wait for CLK_PER;
                 check_true(done = '0', "should not be done after load");

diff --git a/hdl/ip/vhd/common/countdown/sims/countdown_th.vhd b/hdl/ip/vhd/common/countdown/sims/countdown_th.vhd
@@ -6,7 +6,7 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+use ieee.numeric_std_unsigned.all;
 
 library vunit_lib;
     context vunit_lib.vunit_context;
@@ -25,7 +25,7 @@ architecture th of countdown_th is
     signal clk      : std_logic := '0';
     signal reset    : std_logic := '1';
 
-    signal dut_count    : unsigned(SIZE - 1 downto 0) := (others => '0');
+    signal dut_count    : std_logic_vector(SIZE - 1 downto 0) := (others => '0');
     signal dut_load     : std_logic := '0';
     signal dut_decr     : std_logic := '0';
     signal dut_clear    : std_logic := '0';