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Support Turin. #134

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merged 1 commit into from
Jul 11, 2024
Merged

Support Turin. #134

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2 changes: 1 addition & 1 deletion rust-toolchain
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
[toolchain]
channel = "nightly-2024-02-09"
channel = "nightly-2024-06-19"
components = [ "rustfmt", "rust-src" ]
2 changes: 1 addition & 1 deletion src/apcb.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -400,7 +400,7 @@ impl<'a> Apcb<'a> {
const ROME_VERSION: u16 = 0x30;
const V3_HEADER_EXT_SIZE: usize =
size_of::<V2_HEADER>() + size_of::<V3_HEADER_EXT>();
pub const MAX_SIZE: usize = 0x5000;
pub const MAX_SIZE: usize = 0x6500;

pub fn header(&self) -> Result<LayoutVerified<&[u8], V2_HEADER>> {
LayoutVerified::<&[u8], V2_HEADER>::new_unaligned_from_prefix(
Expand Down
109 changes: 91 additions & 18 deletions src/entry.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -439,6 +439,7 @@ impl<'a> schemars::JsonSchema for EntryItem<'a> {
gen: &mut schemars::gen::SchemaGenerator,
) -> schemars::schema::Schema {
use crate::fch;
use crate::gnb;
use crate::memory;
use crate::psp;
use crate::tokens_entry::TokensEntryItem;
Expand Down Expand Up @@ -502,14 +503,14 @@ impl<'a> schemars::JsonSchema for EntryItem<'a> {
"Ddr5CaPinMapElement".to_owned(),
<Vec<memory::Ddr5CaPinMapElement>>::json_schema(gen),
);
obj.properties.insert(
"MemDfeSearchElement20".to_owned(),
<Vec<memory::MemDfeSearchElement20>>::json_schema(gen),
);
obj.properties.insert(
"MemDfeSearchElement32".to_owned(),
<Vec<memory::MemDfeSearchElement32>>::json_schema(gen),
);
obj.properties.insert(
"MemDfeSearchElement36".to_owned(),
<Vec<memory::MemDfeSearchElement36>>::json_schema(gen),
);
obj.properties.insert(
"DdrDqPinMapElement".to_owned(),
<Vec<memory::DdrDqPinMapElement>>::json_schema(gen),
Expand Down Expand Up @@ -544,6 +545,22 @@ impl<'a> schemars::JsonSchema for EntryItem<'a> {
);
obj.properties
.insert("EspiInit".to_owned(), <fch::EspiInit>::json_schema(gen));
obj.properties.insert(
"PmuBistVendorAlgorithmElement".to_owned(),
<Vec<memory::PmuBistVendorAlgorithmElement>>::json_schema(gen),
);
obj.properties.insert(
"Ddr5RawCardConfigElement".to_owned(),
<Vec<memory::Ddr5RawCardConfigElement>>::json_schema(gen),
);
obj.properties.insert(
"EspiSioInitElement".to_owned(),
<Vec<fch::EspiSioInitElement>>::json_schema(gen),
);
obj.properties.insert(
"EarlyPcieConfigElement".to_owned(),
<Vec<gnb::EarlyPcieConfigElement>>::json_schema(gen),
);
obj.properties
.insert("BoardIdGettingMethodGpio".to_owned(),
<(psp::BoardIdGettingMethodGpio,
Expand Down Expand Up @@ -607,6 +624,7 @@ impl<'a> Serialize for EntryItem<'a> {
{
use crate::df::SlinkConfig;
use crate::fch;
use crate::gnb;
use crate::memory;
use crate::psp;
let mut state = serializer.serialize_struct("EntryItem", 2)?;
Expand Down Expand Up @@ -659,12 +677,12 @@ impl<'a> Serialize for EntryItem<'a> {
} else if let Some(s) = self.body_as_struct_array::<memory::Ddr5CaPinMapElement>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("Ddr5CaPinMapElement", &v)?;
} else if let Some(s) = self.body_as_struct_array::<memory::MemDfeSearchElement20>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("MemDfeSearchElement20", &v)?;
} else if let Some(s) = self.body_as_struct_array::<memory::MemDfeSearchElement32>() {
// } else if let Some(s) = self.body_as_struct_array::<memory::MemDfeSearchElement32>() { // UH OH
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UH OH?

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@daym daym May 28, 2024 •
edited
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Yeah. There seem to be two different versions of struct MemDfeSearchElement in use (the number is the size in bytes in decimal).

Since those structs are used in a struct array and there's only a total_size of the entire array somewhere it could (and did) happen that it's misdetected since it's possible that sizeof(MemDfeSearchElement32) divides total_size and also sizeof(MemDfeSearchElement36) divides total_size at the same time (for example total_size = 288 or 576 or 864 or ...). Which struct definition should then be used?

This means that the dump functionality could pick up the wrong struct definition.
It also makes me wonder how Abl knows which one it is when booting.

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Analysis of what we have: 19 of 54 directories in fluffy-tribble do not have that struct size = 36.

Details: Only the following fail assert sizeof == 36:

./am5-1.0.0.6/AgesaPkg/Addendum/Apcb/RaphaelAm5/ApcbDataDefaultRecovery/CRB_Splinter
./am5-1.0.0.6/AgesaPkg/Addendum/Apcb/RaphaelAm5Alt1/ApcbDataDefaultRecovery/CRB_Shredder
./genoa-1.0.0.3/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon
./genoa-1.0.0.3/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby
./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon
./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Cinnabar
./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby
./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Sunstone
./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon
./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Cinnabar
./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby
./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby
./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Sunstone
./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon
./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Cinnabar
./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby
./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Sunstone
./genoa-1.0.0.8/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon
./genoa-1.0.0.8/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby

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@daym daym May 28, 2024 •
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Used struct sizes of that struct are (... they've got to be kidding me):

Size/B HeaderSize/B PayloadSize/B name struct_dir PayloadExtSize/B
36 12 12 ./turin-0.0.7.3/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.7.3/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.7.3/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
36 12 12 ./turin-0.0.7.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.7.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Onyx 12
36 12 12 ./turin-0.0.7.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.7.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Galena 12
36 12 12 ./turin-0.0.7.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
36 12 12 ./turin-0.0.7.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.7.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Onyx 12
36 12 12 ./turin-0.0.7.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.7.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Galena 12
36 12 12 ./turin-0.0.7.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
36 12 12 ./turin-0.0.8.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.8.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.8.0/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
24 12 12 ./am5-1.0.0.6/AgesaPkg/Addendum/Apcb/RaphaelAm5/ApcbDataDefaultRecovery/CRB_Splinter 0
24 12 12 ./am5-1.0.0.6/AgesaPkg/Addendum/Apcb/RaphaelAm5Alt1/ApcbDataDefaultRecovery/CRB_Shredder 0
36 12 12 ./turin-0.0.8.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.8.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.8.1/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
36 12 12 ./turin-0.0.7.2/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.7.2/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.7.2/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
36 12 12 ./am5-1.1.7.0/AGESA/AgesaPkg/Addendum/Apcb/RaphaelAm5/ApcbDataDefaultRecovery/CRB_Splinter 12
36 12 12 ./am5-1.1.7.0/AGESA/AgesaPkg/Addendum/Apcb/GraniteRidgeAm5Alt1/ApcbDataDefaultRecovery/CRB_Shredder 12
36 12 12 ./am5-1.1.7.0/AGESA/AgesaPkg/Addendum/Apcb/GraniteRidgeAm5/ApcbDataDefaultRecovery/CRB_Splinter 12
36 12 12 ./am5-1.1.7.0/AGESA/AgesaPkg/Addendum/Apcb/RaphaelAm5Alt1/ApcbDataDefaultRecovery/CRB_Shredder 12
36 12 12 ./fire-range-0.0.6.0/AGESA/AgesaPkg/Addendum/Apcb/GraniteRidgeFl1/ApcbDataDefaultRecovery/CRB_Vortex 12
20 8 12 ./genoa-1.0.0.3/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon 0
20 8 12 ./genoa-1.0.0.3/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby 0
32 8 12 ./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon 12
32 8 12 ./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Cinnabar 12
32 8 12 ./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
32 8 12 ./genoa-1.0.0.9/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Sunstone 12
36 12 12 ./turin-0.0.7.4/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.7.4/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/BreithornCommon 12
36 12 12 ./turin-0.0.7.4/AgesaPkg/Addendum/Apcb/TurinSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
36 12 12 ./turin-0.0.7.4/AgesaPkg/Addendum/Apcb/VeniceSp7Rdimm/ApcbDataDefaultRecovery/Purico 12
36 12 12 ./turin-0.0.7.4/AgesaPkg/Addendum/Apcb/VeniceSp7Rdimm/ApcbDataDefaultRecovery/WeisshornCommon 12
36 12 12 ./turin-0.0.7.4/AgesaPkg/Addendum/Apcb/VeniceSp7Rdimm/ApcbDataDefaultRecovery/Ruby 12
32 8 12 ./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon 12
32 8 12 ./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Cinnabar 12
32 8 12 ./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
32 8 12 ./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
32 8 12 ./genoa-1.0.0.a/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Sunstone 12
32 8 12 ./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon 12
32 8 12 ./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Cinnabar 12
32 8 12 ./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12
32 8 12 ./genoa-1.0.0.b/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Sunstone 12
36 12 12 ./am5-1.1.0.2b/AGESA/AgesaPkg/Addendum/Apcb/RaphaelAm5/ApcbDataDefaultRecovery/CRB_Splinter 12
36 12 12 ./am5-1.1.0.2b/AGESA/AgesaPkg/Addendum/Apcb/RaphaelAm5Alt1/ApcbDataDefaultRecovery/CRB_Shredder 12
32 8 12 ./genoa-1.0.0.8/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/GenoaCommon 12
32 8 12 ./genoa-1.0.0.8/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm/ApcbDataDefaultRecovery/Ruby 12

// let v = s.iter().collect::<Vec<_>>();
// state.serialize_field("MemDfeSearchElement32", &v)?;
} else if let Some(s) = self.body_as_struct_array::<memory::MemDfeSearchElement36>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("MemDfeSearchElement32", &v)?;
state.serialize_field("MemDfeSearchElement36", &v)?;
} else if let Some(s) = self.body_as_struct_array::<memory::DdrDqPinMapElement>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("DdrDqPinMapElement", &v)?;
Expand Down Expand Up @@ -701,6 +719,18 @@ impl<'a> Serialize for EntryItem<'a> {
state.serialize_field("BoardIdGettingMethodCustom", &t)?;
} else if let Some((header, _)) = self.body_as_struct::<fch::EspiInit>() {
state.serialize_field("EspiInit", &header)?;
} else if let Some(s) = self.body_as_struct_array::<memory::PmuBistVendorAlgorithmElement>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("PmuBistVendorAlgorithmElement", &v)?;
} else if let Some(s) = self.body_as_struct_array::<memory::Ddr5RawCardConfigElement>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("Ddr5RawCardConfigElement", &v)?;
} else if let Some(s) = self.body_as_struct_array::<fch::EspiSioInitElement>() { // TODO terminator, so variant
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("EspiSioInitElement", &v)?;
} else if let Some(s) = self.body_as_struct_array::<gnb::EarlyPcieConfigElement>() {
let v = s.iter().collect::<Vec<_>>();
state.serialize_field("EarlyPcieConfigElement", &v)?;
} else if let Some(s) =
self.body_as_struct_sequence::<memory::platform_specific_override::ElementRef<'_>>() {
let i = s.iter().unwrap();
Expand Down Expand Up @@ -896,9 +926,11 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
LrMaxFreqElement,
DdrDqPinMapElement,
Ddr5CaPinMapElement,
MemDfeSearchElement20,
MemDfeSearchElement32,
MemDfeSearchElement36,
RdimmDdr5BusElement,
EspiSioInitElement, // FIXME move to struct sequence (maybe)
EarlyPcieConfigElement,

// Body as struct
ConsoleOutControl,
Expand All @@ -911,6 +943,8 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
BoardIdGettingMethodSmbus,
BoardIdGettingMethodCustom,
EspiInit,
PmuBistVendorAlgorithmElement,
Ddr5RawCardConfigElement,

// struct sequence
PlatformSpecificOverrides,
Expand All @@ -933,9 +967,11 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
"LrMaxFreqElement",
"DdrDqPinMapElement",
"Ddr5CaPinMapElement",
"MemDfeSearchElement20",
"MemDfeSearchElement32",
"MemDfeSearchElement36",
"RdimmDdr5BusElement",
"EspiSioInitElement",
"EarlyPcieConfigElement",
// Body as struct
"ConsoleOutControl",
"ExtVoltageControl",
Expand All @@ -947,6 +983,8 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
"BoardIdGettingMethodSmbus",
"BoardIdGettingMethodCustom",
"EspiInit",
"PmuBistVendorAlgorithmElement",
"Ddr5RawCardConfigElement",
// struct sequence
"platform_specific_overrides",
"platform_tuning",
Expand Down Expand Up @@ -1015,15 +1053,21 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
"Ddr5CaPinMapElement" => {
Ok(Field::Ddr5CaPinMapElement)
}
"MemDfeSearchElement20" => {
Ok(Field::MemDfeSearchElement20)
}
"MemDfeSearchElement32" => {
Ok(Field::MemDfeSearchElement32)
}
"MemDfeSearchElement36" => {
Ok(Field::MemDfeSearchElement36)
}
"RdimmDdr5BusElement" => {
Ok(Field::RdimmDdr5BusElement)
}
"EspiSioInitElement" => {
Ok(Field::EspiSioInitElement)
}
"EarlyPcieConfigElement" => {
Ok(Field::EarlyPcieConfigElement)
}

"ConsoleOutControl" => Ok(Field::ConsoleOutControl),
"ExtVoltageControl" => Ok(Field::ExtVoltageControl),
Expand All @@ -1047,6 +1091,12 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
Ok(Field::BoardIdGettingMethodCustom)
}
"EspiInit" => Ok(Field::EspiInit),
"PmuBistVendorAlgorithmElement" => {
Ok(Field::PmuBistVendorAlgorithmElement)
}
"Ddr5RawCardConfigElement" => {
Ok(Field::Ddr5RawCardConfigElement)
}
"platform_specific_overrides" => {
Ok(Field::PlatformSpecificOverrides)
}
Expand Down Expand Up @@ -1082,6 +1132,7 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
{
use crate::df;
use crate::fch;
use crate::gnb;
use crate::memory;
use crate::psp;
let mut header: Option<ENTRY_HEADER> = None;
Expand Down Expand Up @@ -1171,15 +1222,15 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
&mut body, &mut map,
)?;
}
Field::MemDfeSearchElement20 => {
Field::MemDfeSearchElement32 => {
struct_vec_to_body::<
memory::MemDfeSearchElement20,
memory::MemDfeSearchElement32,
V,
>(&mut body, &mut map)?;
}
Field::MemDfeSearchElement32 => {
Field::MemDfeSearchElement36 => {
struct_vec_to_body::<
memory::MemDfeSearchElement32,
memory::MemDfeSearchElement36,
V,
>(&mut body, &mut map)?;
}
Expand Down Expand Up @@ -1239,6 +1290,28 @@ impl<'de> Deserialize<'de> for SerdeEntryItem {
&mut body, &mut map,
)?;
}
Field::PmuBistVendorAlgorithmElement => {
struct_vec_to_body::<
memory::PmuBistVendorAlgorithmElement,
V,
>(&mut body, &mut map)?;
}
Field::Ddr5RawCardConfigElement => {
struct_vec_to_body::<
memory::Ddr5RawCardConfigElement,
V,
>(&mut body, &mut map)?;
}
Field::EspiSioInitElement => {
struct_vec_to_body::<fch::EspiSioInitElement, V>(
&mut body, &mut map,
)?;
}
Field::EarlyPcieConfigElement => {
struct_vec_to_body::<gnb::EarlyPcieConfigElement, V>(
&mut body, &mut map,
)?;
}

Field::PlatformSpecificOverrides => {
struct_sequence_to_body::<
Expand Down
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