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Support Genoa #123

Merged
merged 18 commits into from
May 1, 2024
Merged

Support Genoa #123

merged 18 commits into from
May 1, 2024

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daym
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@daym daym commented Apr 8, 2024

Fixes #110.

Successfully tested on opal.

@daym daym requested review from luqmana and dancrossnyc April 8, 2024 23:10
@daym daym self-assigned this Apr 8, 2024
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Wooo thanks for updating this! I took a look at the commits besides my own and they look good mostly. Just some questions about FIXMEs/TODOs left in the code

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src/ondisk.rs Outdated
Comment on lines 4750 to 4764
// XXX: Not that useful.
impl Default for DdrDqPinMapElementLane {
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Can we drop this impl then or is it actually used somewhere?

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@daym daym Apr 29, 2024

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No--since it is used.

It's a design limitation of the impl_struct_serde_conversion macro.

The reason is if we have a struct like this

   struct X {
     a: u32,
     b: u32,
   }

... and then build an instance up like this (which is what impl_struct_serde_conversion does):

    X::builder().with_a(3).with_b(4).build()

... it actually returns an instance of X at X::builder() already. That means it has to default it--what would be the values of a and b otherwise? Even let's say we avoided that somehow, what's the value of the expression X::builder().with_a(3) ? Remember that X is the actual memory-mapped AMD struct--so we can't just change it to make all fields optional or something.

This could be avoided by having some (smarter) intermediate builder struct--but most of the time you really DO want defaults anyway.

In the specific case of DdrDqPinMapElementLane you want to use all 32 possible values but then you'd repeat them again anyhow--so it's not clear how to materially improve the accessors or validation.

src/ondisk.rs Outdated
#[derive(FromBytes, AsBytes, Unaligned, PartialEq, Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct Ddr5CaPinMapElementLane {
pins: [u8; 14], // TODO: nicer pin type instead of u8; especially for 0xff "un"
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Maybe a general clean memory types clean up issue to link with these TODOs.

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@dancrossnyc
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I have much the same questions as Luqman. Also, we should rename the lone WIP commit to something that's not a WIP.

@daym daym force-pushed the issue-110 branch 2 times, most recently from 6735d0d to 596a131 Compare April 29, 2024 22:14
@daym daym requested a review from luqmana April 29, 2024 22:25
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Thanks for updating this @daym! Looks like there are SerdeHex related errors breaking CI. Pending that I think we can merge this and address tagged issues in follow up

@daym daym force-pushed the issue-110 branch 2 times, most recently from ce31b34 to a76f2dd Compare May 1, 2024 21:38
@daym daym merged commit 5a35018 into main May 1, 2024
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@daym daym deleted the issue-110 branch May 1, 2024 22:00
@belotv
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belotv commented Jul 17, 2024

Hi, this breaks compatibility with several CPU families (at least Renoir/Cezanne), which use "BCBA" as signature ending (not sure it was fully compatible before but after this commit it is definitely not).

Confirmed: Renoir/Cezanne did work before this commit.

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Support Genoa
4 participants