Skip to content
View out-of-order55's full-sized avatar
  • ICer in Southeast University
  • WuHan

Block or report out-of-order55

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
out-of-order55/README.md

My github stats

⚡ 我的技术栈 | My Tech Stack

  • systemverilog verilog c python

  • verilator quartus vivado

Pinned Loading

  1. booth-multiplier booth-multiplier Public

    基4booth乘法器设计与验证

    VHDL 8

  2. DCache DCache Public

    2 way|PLRU|2*4k

    SystemVerilog 5

  3. SRT-Divider SRT-Divider Public

    简单的未优化的SRT除法器

    Verilog 5

  4. cache-sim cache-sim Public

    一个可配置的cachesim

    C 1

  5. ysyx-question ysyx-question Public

    一生一芯必答题

    1

  6. prefetcher-sim prefetcher-sim Public

    A sim has l1 and l2 cache

    Python 2