Merge pull request #168 from RapidSilicon/ocla_parameter_fix

Update axil_ocla_litex_wrapper.py
os-fpga · Aug 25, 2023 · ef5d6b5 · ef5d6b5
2 parents f3bee28 + 9493f6c
commit ef5d6b5
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py b/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py
@@ -65,6 +65,7 @@ def __init__(self, platform,
             # -----------  
             p_IP_TYPE                 = Instance.PreformattedParam("IP_TYPE"),
             p_IP_ID                   = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION              = Instance.PreformattedParam("IP_VERSION"),
             p_NO_OF_PROBES            = Instance.PreformattedParam(nprobes),
             p_NO_OF_TRIGGER_INPUTS    = Instance.PreformattedParam(trigger_inputs),
             p_PROBE_WIDHT             = Instance.PreformattedParam(probe_widht),