Merge branch 'delays_comb' of github.com:os-fpga/IP_Catalog into dela…

…ys_comb

.github/workflows/main.yml

@@ -48,7 +48,7 @@ jobs:
         
         cd Raptor_Tools/python_tools/build/share/envs/litex/bin
         
-        excluded_ips=("on_chip_memory" "axil_quadspi" "ahb2axi_bridge" "axi2axilite_bridge" "axis_width_converter" "i2c_master" "axil_ethernet")
+        excluded_ips=("on_chip_memory" "axil_quadspi" "ahb2axi_bridge" "axi2ahb_bridge" "axi2axilite_bridge" "axis_width_converter" "i2c_master" "axil_ethernet")
         simulation_list=( "axi fifo" "dsp_generator" "axi_ram" "axi2axilite_bridge" "fifo_generator" "axis_ram_switch" "axis_switch" "axis_broadcast" "axis_uart" "axis_adapter" "i2c_master" "i2c_slave")
         #fix ethernet ip        
         for n in $gen_list

rapidsilicon/README.md

@@ -23,6 +23,7 @@ IP Catalog is an IP library for Raptor toolchain.
 			ip/
 			├── ahb2axi_bridge
 			├── ahb_sram
+			├── axi2ahb_bridge
 			├── axi2axilite_bridge
 			├── axi_async_fifo
 			├── axi_cdma

rapidsilicon/ip/axi2ahb_bridge/v1_0/LICENSE

@@ -0,0 +1,50 @@
+
+COPYRIGHT TEXT:
+--------------
+
+Copyright (c) 2022 RapidSilicon
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 
+the Software, and to permit persons to whom the Software is furnished to do so, 
+subject to the following conditions: The above copyright notice and this 
+permission notice shall be included in all copies or substantial portions of the
+Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+FILES:
+rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py
+rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py
+
+---------------------------------------------------------------------------------------
+
+COPYRIGHT TEXT:
+--------------
+
+Copyright 2019-2022  Gisselquist Technology, LLC
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+FILES:
+rapidsilicon/ip/ahb2axi_bridge/v1_0/src/ahb2axi4.sv
+rapidsilicon/ip/ahb2axi_bridge/v1_0/src/beh_lib.sv
+
+---------------------------------------------------------------------------------------

rapidsilicon/ip/axi2ahb_bridge/v1_0/README.md

@@ -0,0 +1,32 @@
+# AHB to AXI4 Brigde IP
+## Introduction
+AHB-to-AXI4 Bridge IP
+
+For more information, visit: https://github.com/westerndigitalcorporation/swerv_eh1/blob/master/design/lib/axi4_to_ahb.sv
+
+## Generator Script
+This directory contains the generator script which places the RTL to `rapidsilicon/ip/ahb2axi_bridge/v1_0/<build-name>/src` directory and generates its wrapper in the same directory. 
+
+## Parameters
+User can configure ahb2axi_bridge CORE using following parameters:
+
+| Sr.No.|      Parameter       |         Keyword        |         Value         |
+|-------|----------------------|------------------------|-----------------------|
+|   1.  |   data_width         |    data_width          |   32-64               |
+|   2.  |   addr_width         |    addr_width          |   6-32                |
+|   3.  |   id_width           |    id_width            |   1-32                |
+
+
+
+To generate RTL with above parameters, run the following command:
+```
+python3 ahb2axi_bridge_gen.py --data_width=32 --addr_width=8 --build-name=wrapper --build
+```
+
+## TCL File
+
+This python script also generates a raptor.tcl file which will be placed in `rapidsilicon/ip/ahb2axi_bridge/v1_0/<build-name>/synth` directory.
+
+
+## References
+https://github.com/westerndigitalcorporation/swerv_eh1/blob/master/design/lib/axi4_to_ahb.sv

rapidsilicon/ip/axi2ahb_bridge/v1_0/axi2ahb_bridge_gen.py

@@ -0,0 +1,221 @@
+#!/usr/bin/env python3
+#
+# This file is Copyright (c) 2022 RapidSilicon.
+#
+# SPDX-License-Identifier: MIT
+
+import os
+import sys
+import logging
+import argparse
+
+from datetime import datetime
+
+from litex_wrapper.axi2ahb_bridge_litex_wrapper import AXI2AHB
+
+from migen import *
+
+from litex.build.generic_platform import *
+
+from litex.build.osfpga import OSFPGAPlatform
+
+from litex.soc.interconnect.axi import AXIInterface, AXILiteInterface
+
+
+# IOs / Interface ----------------------------------------------------------------------------------
+def get_clkin_ios():
+    return [
+        ("s_axi_aclk",      0, Pins(1)),
+        ("s_axi_aresetn",   0, Pins(1))]
+
+
+def ahb_interface(addr_width,data_width):
+    return [
+
+        ("ahb_haddr",   	0, Pins(addr_width)),
+        ("ahb_hburst",   	0, Pins(3)),
+        ("ahb_hmastlock",   0, Pins(1)),
+        ("ahb_hprot",   	0, Pins(4)),
+        ("ahb_hsize",  	    0, Pins(3)),
+        ("ahb_htrans",  	0, Pins(2)),
+        ("ahb_hwrite",  	0, Pins(1)),
+        ("ahb_hwdata",  	0, Pins(data_width)),
+        ("ahb_hsel",  		0, Pins(1)),
+        ("ahb_hnonsec",  	0, Pins(1)),
+        ("ahb_hrdata",  	0, Pins(data_width)),
+        ("ahb_hready",  	0, Pins(1)),
+        ("ahb_hresp",  	    0, Pins(1)),
+    ]
+
+# AHB-2-AXI4 Wrapper --------------------------------------------------------------------------------
+class AXI2AHBWrapper(Module):
+    def __init__(self, platform, data_width, addr_width, id_width):
+
+        # Clocking
+        platform.add_extension(get_clkin_ios())
+        self.clock_domains.cd_sys = ClockDomain()
+        self.comb += self.cd_sys.clk.eq(platform.request("s_axi_aclk"))
+        self.comb += self.cd_sys.rst.eq(platform.request("s_axi_aresetn"))
+
+
+        # AXI MASTER PORT
+        s_axi = AXIInterface(
+            data_width      = data_width,
+            address_width   = addr_width,
+            id_width        = id_width
+        )
+
+
+        platform.add_extension(s_axi.get_ios("s_axi"))
+        self.comb += s_axi.connect_to_pads(platform.request("s_axi"), mode="slave")
+
+        # AXI_2_AHB
+        self.submodules.axi2ahb = axi2ahb = AXI2AHB(platform, s_axi)
+
+        platform.add_extension(ahb_interface(addr_width,data_width))
+
+        self.comb += platform.request("ahb_haddr").eq(axi2ahb.ahb_haddr)
+        self.comb += platform.request("ahb_hburst").eq(axi2ahb.ahb_hburst)
+        self.comb += platform.request("ahb_hmastlock").eq(axi2ahb.ahb_hmastlock)
+        self.comb += platform.request("ahb_hprot").eq(axi2ahb.ahb_hprot)
+        self.comb += platform.request("ahb_hsize").eq(axi2ahb.ahb_hsize)
+        self.comb += platform.request("ahb_htrans").eq(axi2ahb.ahb_htrans)
+        self.comb += platform.request("ahb_hwrite").eq(axi2ahb.ahb_hwrite)
+        self.comb += platform.request("ahb_hwdata").eq(axi2ahb.ahb_hwdata)
+
+
+        self.comb += axi2ahb.ahb_hrdata.eq(platform.request("ahb_hrdata"))
+        self.comb += axi2ahb.ahb_hready.eq(platform.request("ahb_hready"))
+        self.comb += axi2ahb.ahb_hresp.eq(platform.request("ahb_hresp"))
+
+
+
+# Build --------------------------------------------------------------------------------------------
+def main():
+    parser = argparse.ArgumentParser(description="AHB_2_AXI4 CORE")
+
+    # Import Common Modules.
+    common_path = os.path.join(os.path.dirname(__file__), "..", "..", "..", "lib")
+    sys.path.append(common_path)
+
+    from common import IP_Builder
+
+    # Parameter Dependency dictionary
+    #                Ports     :    Dependency
+    dep_dict = {}            
+
+    # IP Builder.
+    rs_builder = IP_Builder(device="gemini", ip_name="axi2ahb_bridge", language="System verilog")
+
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
+    # Core fix value parameters.
+    core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
+    core_fix_param_group.add_argument("--data_width",       type=int,       default=32,         choices=[32, 64],      help="Data Width")
+
+    # Core range value parameters.
+    core_range_param_group = parser.add_argument_group(title="Core range parameters")
+    core_range_param_group.add_argument("--addr_width",     type=int,       default=32,      choices=range(6, 33),      help="Address Width")
+    core_range_param_group.add_argument("--id_width",       type=int,       default=1,      choices=range(1, 33),      help="ID Width")
+
+    # Build Parameters.
+    build_group = parser.add_argument_group(title="Build parameters")
+    build_group.add_argument("--build",         action="store_true",            help="Build Core")
+    build_group.add_argument("--build-dir",     default="./",                   help="Build Directory")
+    build_group.add_argument("--build-name",    default="axi2ahb_wrapper",     help="Build Folder Name, Build RTL File Name and Module Name")
+
+    # JSON Import/Template
+    json_group = parser.add_argument_group(title="JSON Parameters")
+    json_group.add_argument("--json",                                    help="Generate Core from JSON File")
+    json_group.add_argument("--json-template",  action="store_true",     help="Generate JSON Template")
+
+    args = parser.parse_args()
+
+   #IP Details generation
+    details =  {   "IP details": {
+    'Name' : 'axi2ahb bridge',
+    'Version' : 'V1_0',
+    'Interface' : 'AHB and AXI',
+    'Description' : 'This bridge acts as a translator and mediator, facilitating seamless data transfer and control signal synchronization between devices or subsystems designed with AHB-based interfaces and those using AXI4-based interfaces.'}}
+
+    # Import JSON (Optional) -----------------------------------------------------------------------
+    if args.json:
+        args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version  = "v1_0")
+
+    #IP Summary generation
+        file_path = os.path.dirname(os.path.realpath(__file__))
+        rs_builder.copy_images(file_path)
+
+    summary =  {  
+    "Data width programmed": args.data_width,
+    "Address width programmed": args.addr_width,
+    "AXI ID width programmed": args.id_width,
+    }
+
+    # Export JSON Template (Optional) --------------------------------------------------------------
+    if args.json_template:
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
+
+
+
+    # Create Wrapper -------------------------------------------------------------------------------
+    platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
+    module   = AXI2AHBWrapper(platform,
+        data_width = args.data_width,
+        addr_width = args.addr_width,
+        id_width   = args.id_width
+    )
+
+    # Build Project --------------------------------------------------------------------------------
+    if args.build:
+        rs_builder.prepare(
+            build_dir  = args.build_dir,
+            build_name = args.build_name,
+            version    = "v1_0"
+        )
+        rs_builder.copy_files(gen_path=os.path.dirname(__file__))
+        rs_builder.generate_tcl(version    = "v1_0")
+        rs_builder.generate_wrapper(
+            platform   = platform,
+            module     = module,
+            version    = "v1_0"
+        )
+
+        # IP_ID Parameter
+        now = datetime.now()
+        my_year         = now.year - 2022
+        year            = (bin(my_year)[2:]).zfill(7) # 7-bits  # Removing '0b' prefix = [2:]
+        month           = (bin(now.month)[2:]).zfill(4) # 4-bits
+        day             = (bin(now.day)[2:]).zfill(5) # 5-bits
+        mod_hour        = now.hour % 12 # 12 hours Format
+        hour            = (bin(mod_hour)[2:]).zfill(4) # 4-bits
+        minute          = (bin(now.minute)[2:]).zfill(6) # 6-bits
+        second          = (bin(now.second)[2:]).zfill(6) # 6-bits
+
+        # Concatenation for IP_ID Parameter
+        ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
+        ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])
+
+        # IP_VERSION parameter
+        #               Base  _  Major _ Minor
+        ip_version = "00000000_00000000_0000000000000001"
+        ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])
+
+        wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axi2ahb_bridge", "v1_0", args.build_name, "src",args.build_name + "_" + "v1_0" + ".v")
+        new_lines = []
+        with open (wrapper, "r") as file:
+            lines = file.readlines()
+            for i, line in enumerate(lines):
+                if ("module {}".format(args.build_name)) in line:
+                    new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"A2HB\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
+                else:
+                    new_lines.append(line)
+
+        with open(os.path.join(wrapper), "w") as file:
+            file.writelines(new_lines)
+
+if __name__ == "__main__":
+    main()