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dly_site_addr issue resolved
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@moinijaz
moinijaz committed Nov 29, 2024
1 parent a7ba8c1 commit b8f7a9c
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2 changes: 1 addition & 1 deletion rapidsilicon/ip/io_configurator/v1_0/src/DLY_ADDR_CNTRL.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ module DLY_ADDR_CNTRL #(parameter NUM_GB_SITES = 20,
input [20-1: 0] usr_dly_ld, // Input from user to control I_DELAY. Only one signal should be active at any time
input [20-1: 0] usr_dly_adj, // Input from user to control I_DELAY
input [20-1: 0] usr_rd_dly_value, // Input from user to read the I_DELAY output port for TAP Value
output reg [ADDR_WIDTH-1:0] f2g_dly_addr, // Address bus to GBox. Selects the I_DELAY
output [ADDR_WIDTH-1:0] f2g_dly_addr, // Address bus to GBox. Selects the I_DELAY
output cntrl_dly_incdec, // Drive the selected I_DELAY INCDEC signal based upon the active user_dly_ld signal
output cntrl_dly_ld, // Drive the selected I_DELAY LD siganl based upon the active user_dly_ld signal
output cntrl_dly_adj, // Drive the selected I_DELAY ADJ siganl based upon the active user_dly_adj signal
Expand Down
89 changes: 54 additions & 35 deletions rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,7 @@ reg [(NUM_GB_SITES*NUM_CNTRL)-1:0] usr_dly_ld;
reg [(NUM_GB_SITES*NUM_CNTRL)-1:0] usr_dly_adj;
reg [(NUM_GB_SITES*NUM_CNTRL)-1:0] usr_dly_incdec;
wire [(DLY_TAP_WIDTH*NUM_GB_SITES*NUM_CNTRL)-1:0] usr_delay_tap_value;
wire [(DLY_TAP_WIDTH*NUM_GB_SITES*NUM_CNTRL)-1:0] dly_tap_value;
reg [(DLY_TAP_WIDTH*NUM_GB_SITES*NUM_CNTRL)-1:0] dly_tap_value;

wire clk_in;
wire lock;
Expand Down Expand Up @@ -226,11 +226,8 @@ wire lock;
`endif

PLL #(
.DIVIDE_CLK_IN_BY_2("FALSE"),
.PLL_MULT(PLL_MULT),
.PLL_DIV(PLL_DIV),
.PLL_MULT_FRAC(0),
.PLL_POST_DIV(2)
.PLL_DIV(PLL_DIV)
)
PLL_inst (
.PLL_EN(1'd1),
Expand Down Expand Up @@ -260,11 +257,11 @@ always @(*) begin
end
end

// wire [DLY_TAP_WIDTH-1:0] dly_tap_val_reg [NUM_DLY-1:0];
// always @(*) begin
// dly_tap_value = 'h0;
// dly_tap_value[(dly_site_addr[SEL_DLY] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH] = dly_tap_val_reg[SEL_DLY];
// end
wire [DLY_TAP_WIDTH-1:0] dly_tap_val_reg [NUM_DLY-1:0];
always @(*) begin
// dly_tap_value = 'h0;
dly_tap_value[(dly_site_addr[SEL_DLY] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH] = dly_tap_val_reg[SEL_DLY];
end

wire [(NUM_CNTRL*ADDR_WIDTH)-1:0] f2g_dly_addr;
wire [NUM_CNTRL-1:0] cntrl_dly_ld;
Expand Down Expand Up @@ -403,7 +400,6 @@ end

`ifdef bidirectional
wire [(NUM_DLY/2)-1:0] i_buf_out;
// wire [(NUM_DLY/2)-1:0] dly_out;

generate
for(genvar i = 0; i < NUM_DLY/2; i = i + 1) begin
Expand Down Expand Up @@ -458,7 +454,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(DOUT_IDLY[i])
);

Expand All @@ -470,7 +467,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -535,7 +533,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(idly_out[i])
);

Expand Down Expand Up @@ -585,7 +584,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -643,7 +643,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(idly_out[i])
);
I_DDR I_DDR_inst (
Expand All @@ -669,7 +670,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -730,7 +732,7 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(DOUT_IDLY[i])
);

Expand Down Expand Up @@ -759,7 +761,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -817,7 +820,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(DOUT_IDLY[i])
);

Expand All @@ -836,7 +840,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -895,7 +900,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(idly_out[i])
);

Expand Down Expand Up @@ -928,7 +934,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -988,7 +995,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(idly_out[i])
);

Expand Down Expand Up @@ -1028,7 +1036,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -1085,7 +1094,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(idly_out[i])
);
I_DDR I_DDR_inst (
Expand All @@ -1104,7 +1114,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -1168,7 +1179,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+0]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+0]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+0]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+0]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+0] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(idly_out[i])
);
I_DDR I_DDR_inst (
Expand Down Expand Up @@ -1204,7 +1216,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[(i*2)+1]]),
.DLY_ADJ(delay_adj[dly_site_addr[(i*2)+1]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[(i*2)+1]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[(i*2)+1]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[(i*2)+1] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);

Expand Down Expand Up @@ -1248,7 +1261,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[i]]),
.DLY_ADJ(delay_adj[dly_site_addr[i]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[i]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[i]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(DATA_OUT[i])
);

Expand Down Expand Up @@ -1286,7 +1300,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[i]]),
.DLY_ADJ(delay_adj[dly_site_addr[i]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[i]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[i]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(dly_out[i])
);
I_SERDES # (
Expand Down Expand Up @@ -1344,7 +1359,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[i]]),
.DLY_ADJ(delay_adj[dly_site_addr[i]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[i]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[i]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(dly_out[i])
);
I_DDR I_DDR_inst (
Expand All @@ -1366,7 +1382,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[i]]),
.DLY_ADJ(delay_adj[dly_site_addr[i]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[i]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[i]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(dly_out[i])
);

Expand Down Expand Up @@ -1422,7 +1439,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[i]]),
.DLY_ADJ(delay_adj[dly_site_addr[i]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[i]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[i]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);
`ifdef SINGLE_ENDED
Expand Down Expand Up @@ -1469,7 +1487,8 @@ generate
.DLY_LOAD(delay_ld_dec_out[dly_site_addr[i]]),
.DLY_ADJ(delay_adj[dly_site_addr[i]]),
.DLY_INCDEC(delay_incdec[dly_site_addr[i]]),
.DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.DLY_TAP_VALUE(dly_tap_val_reg[i]),
// .DLY_TAP_VALUE(dly_tap_value[(dly_site_addr[i] * DLY_TAP_WIDTH) +: DLY_TAP_WIDTH]),
.O(odly_out[i])
);
`ifdef SINGLE_ENDED
Expand Down
4 changes: 2 additions & 2 deletions rapidsilicon/ip/io_configurator/v1_0/src/header.vh
View file
Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
`define RX_CLOCK
`define IO_DELAY
`define I_DELAY
`define I_DELAY
`define SINGLE_ENDED

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