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fixed ocla conflicts
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@moinijaz-RS
moinijaz-RS committed Aug 23, 2023
2 parents 7fee3d7 + 59fd7aa commit 8bb331c
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Showing 8 changed files with 1,441 additions and 1,385 deletions.
24 changes: 18 additions & 6 deletions .github/workflows/main.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -52,19 +52,31 @@ jobs:
shell: bash
run: |
gen_list=`find $GITHUB_WORKSPACE/rapidsilicon/ip -type f -iname "*_gen.py"`
cd Raptor_Tools/python_tools/build/share/envs/litex/bin
excluded_ips=("axil_quadspi" "ahb2axi_bridge" "axi2axilite_bridge" "axis_width_converter" "i2c_master" "axil_ethernet" "fifo_generator" "dsp_generator")
#fix ethernet ip
for n in $gen_list
do
./python3 $n --build --json-template
ip_name=$(basename "${n%_gen.py}")
echo $ip_name
find /home/runner/work/IP_Catalog/IP_Catalog/Raptor_Tools/python_tools/build/share/envs/litex/bin -type f -name $ip_name"_wrapper.v"
echo "IP generated RTL generated"
done
#file_path=$(find /home/runner/work/IP_Catalog/IP_Catalog/Raptor_Tools/python_tools/build/share/envs/litex/bin -type f -name $ip_name"_wrapper.v")
file_path=$(find /home/runner/work/IP_Catalog/IP_Catalog/Raptor_Tools/python_tools/build/share/envs/litex/bin -type f -name "${ip_name}_wrapper.v" -o -name "${ip_name}_wrapper.sv")
# Check if the IP name is in the excluded_ips array
if [[ ! " ${excluded_ips[@]} " =~ " $ip_name " ]]; then
if [[ -n "$file_path" ]]; then
echo "Success! IP RTL generated at: $file_path"
else
echo "IP RTL wrapper not generated. Exiting."
exit 1
fi
else
echo "Skipping wrapper check for $ip_name"
fi
done
- name: Test IP Generation
run: |
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3 changes: 1 addition & 2 deletions rapidsilicon/ip/axil_ocla/v1_0/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,7 @@ User can enable different OCLA IP Core features using the following Macros:
| Sr.No.| Feature | Macro | Description |
|-------|-----------------------------|--------------------------------|----------------------------------|
| 1. | Value Compare Feature | value_compare | To enable Value Compare feature |
| 2. | Advance Trigger Mode | advance_trigger | To enable Advance Trigger Mode |
| 3. | Enable Trigger Inputs | trigger_inputs_en | To enable Trigger inputs |
| 2. | Enable Trigger Inputs | trigger_inputs_en | To enable Trigger inputs |

To generate RTL with above parameters, run the following command:
```
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88 changes: 54 additions & 34 deletions rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,8 @@
import json
import argparse

from datetime import datetime

from litex_wrapper.axil_ocla_litex_wrapper import AXILITEOCLA

from migen import *
Expand All @@ -36,7 +38,7 @@ def get_samplingclknrst_ios():

def get_ocla_ios(nprobes,trigger_inputs):
return [
("i_probes", 0, Pins(nprobes)),
("i_probes", 0, Pins(nprobes)),
("i_trigger_input", 0, Pins(trigger_inputs)),
]

Expand Down Expand Up @@ -83,7 +85,6 @@ def __init__(self, platform, address_width, data_width, nprobes, trigger_inputs,
if(trigger_inputs_en == True):
self.comb += ocla.trigger_input_i.eq(platform.request("i_trigger_input"))


# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="AXI LITE OCLA CORE")
Expand All @@ -108,9 +109,9 @@ def main():

# Core fix value parameters.
core_fix_param_group = parser.add_argument_group(title="OCLA IP Core fix parameters")
core_fix_param_group.add_argument("--mem_depth", type=int, default=32, choices=[32, 64, 128, 256, 512, 1024], help="OCLA Trace Memory Depth.")
core_fix_param_group.add_argument("--s_axi_addr_width", type=int, default=32, choices=[8, 16, 32], help="OCLA Address Width.")
core_fix_param_group.add_argument("--s_axi_data_width", type=int, default=32, choices=[32], help="OCLA Data Width.")
core_fix_param_group.add_argument("--mem_depth", type=int, default=32, choices=[32, 64, 128, 256, 512, 1024], help="OCLA Trace Memory Depth.")
core_fix_param_group.add_argument("--s_axi_addr_width", type=int, default=32, choices=[8, 16, 32], help="OCLA Address Width.")
core_fix_param_group.add_argument("--s_axi_data_width", type=int, default=32, choices=[32], help="OCLA Data Width.")

# Core range value parameters.
core_range_param_group = parser.add_argument_group(title="OCLA IP Core range parameters")
Expand All @@ -121,16 +122,21 @@ def main():
core_bool_param_group.add_argument("--value_compare", type=bool, default=False, help="To enable Value Compare feature")
core_range_param_group.add_argument("--value_compare_probe_width", type=int, default=1, choices=range(1, 32), help="Width of probe for Value Compare. Only applicable when value compare feature is enable")

core_bool_param_group.add_argument("--trigger_inputs_en", type=bool, default=False, help="To enable Trigger inputs")
core_range_param_group.add_argument("--no_of_trigger_inputs", type=int, default=1, choices=range(1,32), help="Number of Input Triggers.")
core_bool_param_group.add_argument("--advance_trigger", type=bool, default=False, help="To enable Advance Trigger Mode")

# Build Parameters.
build_group = parser.add_argument_group(title="Build parameters")
build_group.add_argument("--build", action="store_true", help="Build Core")
build_group.add_argument("--build-dir", default="./", help="Build Directory")
build_group.add_argument("--build-name", default="axil_ocla_wrapper", help="Build Folder Name, Build RTL File Name and Module Name")

# Core bool value macros.
core_bool_param_group = parser.add_argument_group(title="OCLA IP Core bool parameters")
core_bool_param_group.add_argument("--value_compare", type=bool, default=False, help="To enable Value Compare feature")
core_range_param_group.add_argument("--value_compare_probe_width", type=int, default=1, choices=range(1, 32), help="Width of probe for Value Compare. Only applicable when value compare feature is enable")

core_bool_param_group.add_argument("--trigger_inputs_en", type=bool, default=False, help="To enable Trigger inputs")
core_range_param_group.add_argument("--no_of_trigger_inputs", type=int, default=1, choices=range(1,32), help="Number of Input Triggers.")
#core_bool_param_group.add_argument("--advance_trigger", type=bool, default=False, help="To enable Advance Trigger Mode")

# JSON Import/Template
json_group = parser.add_argument_group(title="JSON Parameters")
json_group.add_argument("--json", help="Generate Core from JSON File")
Expand Down Expand Up @@ -159,7 +165,7 @@ def main():
)
# Arguments ----------------------------------------------------------------------------
value_compare = args.value_compare
advance_trigger = args.advance_trigger
# advance_trigger = args.advance_trigger
triginpts_en = args.trigger_inputs_en
nofprobes = args.no_of_probes
ntrigger_inputs = args.no_of_trigger_inputs
Expand All @@ -179,30 +185,44 @@ def main():
platform = platform,
module = module,
)
# Update the macro definition file ---------------------------------------------------------
#rtl_dir = os.path.join(os.path.dirname(__file__),rs_builder.src_path+"/ocla.sv")
rtl_dir = rs_builder.src_path
rtl_dir = rtl_dir + "/ocla.sv"
f = open(rtl_dir,"r+")
content = f.read()
f.seek(0, 0)
f.write("// ---------------------------------------------------------------\n")
f.write("// User specified macros\n")
f.write("// ---------------------------------------------------------------\n")
f.write("`define NUM_OF_PROBES " + str(nofprobes) +"\n")
f.write("`define MEMORY_DEPTH " + str(memory_depth) +"\n")
f.write("`define NUM_OF_TRIGGER_INPUTS "+ str(ntrigger_inputs)+"\n")
f.write("`define PROBE_WIDHT_BITS "+ str(nprobe_widht)+"\n")
if(value_compare):
f.write("`define VALUE_COMPARE_TRIGGER \n")
if(triginpts_en):
f.write("`define TRIGGER_INPUTS \n")
if(advance_trigger):
f.write("`define ADVANCE_TRIGGER \n\n")
f.write(content)
f.close()



# IP_ID Parameter
now = datetime.now()
my_year = now.year - 2022
year = (bin(my_year)[2:]).zfill(7) # Removing '0b' prefix
month = (bin(now.month)[2:]).zfill(4) # 4-bits
day = (bin(now.day)[2:]).zfill(5) # 5-bits
hour = (now.hour) # 8-bits
minute = (now.minute) # 8-bits

if minute in range(10):
minute = ("0{}".format(minute))

if hour in range(10):
hour = ("0{}".format(hour))

# Concatenation for IP_ID Parameter
ip_id = ("{}{}{}".format(year, day, month))
ip_id = ("32'h{}{}{}").format((hex(int(ip_id, 2))[2:]), hour, minute)

# IP_VERSION parameter
# Base _ Major _ Minor
ip_version = "00000000_00000000_0000000000000001"
ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])

wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axil_ocla", "v1_0", args.build_name, "src",args.build_name+".sv")
new_lines = []
with open (wrapper, "r") as file:
lines = file.readlines()
for i, line in enumerate(lines):
if ("module {}".format(args.build_name)) in line:
new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"ocla\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
else:
new_lines.append(line)

with open(os.path.join(wrapper), "w") as file:
file.writelines(new_lines)

if __name__ == "__main__":
main()

14 changes: 8 additions & 6 deletions rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py
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Original file line number Diff line number Diff line change
Expand Up @@ -64,9 +64,10 @@ def __init__(self, platform,
# Module instance.
# ----------------
self.specials += Instance("ocla",

# Parameters.
# -----------
# Parameters.
# -----------
p_IP_TYPE = Instance.PreformattedParam("IP_TYPE"),
p_IP_ID = Instance.PreformattedParam("IP_ID"),
p_NO_OF_PROBES = Instance.PreformattedParam(nprobes),
p_NO_OF_TRIGGER_INPUTS = Instance.PreformattedParam(trigger_inputs),
p_PROBE_WIDHT = Instance.PreformattedParam(probe_widht),
Expand Down Expand Up @@ -123,9 +124,10 @@ def __init__(self, platform,

else:
self.specials += Instance("ocla",

# Parameters.
# -----------
# Parameters.
# -----------
p_IP_TYPE = Instance.PreformattedParam("IP_TYPE"),
p_IP_ID = Instance.PreformattedParam("IP_ID"),
p_NO_OF_PROBES = Instance.PreformattedParam(nprobes),
p_NO_OF_TRIGGER_INPUTS = Instance.PreformattedParam(trigger_inputs),
p_PROBE_WIDHT = Instance.PreformattedParam(probe_widht),
Expand Down
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