added block diagram, details and summary for UI backend implementation

rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py

@@ -233,9 +233,17 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXI Direct Memory Access',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI4, AXI-Stream',
+    'Description' : 'The AXI DMA soft IP facilitates seamless, high-speed data transfer between memory and peripherals bypassing any CPU, enhancing overall FPGA system efficiency and performance. This IP core simplifies complex data handling tasks, making it a valuable addition to various FPGA designs.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
 
         if (args.axis_id_enable == False):
             dep_dict.update({
@@ -263,10 +271,22 @@ def main():
             })        
 
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+
+    summary =  { 
+    "AXI Data Width": args.axi_data_width,
+    "AXI Address Width": args.axi_addr_width,
+    "Read Descriptor Input": "AXI",
+    "Read Descriptor Status Output": "AXI",
+    "Read Data Output": "AXI-Stream",
+    "Write Descriptor Input" : "AXI",
+    "Write Descriptor Status Output": "AXI",
+    "Write Data Input" : "AXI-Stream",
+    "Master Interface" : "AXI"
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py

@@ -103,13 +103,27 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXILite GPIO',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI-Lite',
+    'Description' : 'GPIO stands for General-Purpose Input/Output. It refers to a type of interface found on microcontrollers and single-board computers that allows them to connect to and interact with a wide variety of external devices.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
+
+    summary =  { 
+    "AXILite Data Width": args.data_width,
+    "AXILite Address Width": args.addr_width,
+    "Interrupt" : "Single bit interrupt supported"
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py

@@ -119,15 +119,31 @@ def main():
     json_group.add_argument("--json-template",  action="store_true",            help="Generate JSON Template")
 
     args = parser.parse_args()
+
+    details =  {   "IP details": {
+    'Name' : 'AXILite UART 16550',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI-Lite',
+    'Description' : 'AXI Lite UART is a type of Universal Asynchronous Receiver-Transmitter (UART) that uses the AXI Lite protocol to interface with other devices in an embedded system. UARTs are commonly used to transmit and receive data between a microcontroller or processor and other devices.'}
+    }
+
 
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
+
+    summary =  { 
+    "AXILite Data Width": args.data_width,
+    "AXILite Address Width": args.addr_width,
+    "AXILite Protection Width": "3",
+    "Registers": "0x00000000 - 0x00000006"
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
-
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
+        
     # Create LiteX Core ----------------------------------------------------------------------------
     platform   = OSFPGAPlatform( io=[], device="gemini", toolchain="raptor")
     module     = AXILITEUARTWrapper(platform,

rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py

@@ -127,9 +127,17 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXI-Stream Broadcast',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI-Streaming',
+    'Description' : 'A Broadcast is a communication protocol for connecting different components of a system in a parallel and synchronized manner. Broadcast allows multiple slaves to receive the same data from a single master at the same time.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
 
         if (args.id_en == False):
             dep_dict.update({
@@ -158,9 +166,15 @@ def main():
 
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
 
+    summary =  { 
+    "AXI-Stream Data Width": args.data_width,
+    "Count of Masters": args.m_count,
+    "AXI-Stream Destination Widht": args.dest_width
+    }
+
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py

@@ -124,13 +124,26 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXI-Stream UART',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI-Streaming',
+    'Description' : 'The AXIS UART is designed to be used with the AXIS bus, which provides a high-speed, low-latency data path between the UART and other components in the system. UARTs are commonly used to transmit and receive data between a microcontroller and processor and other devices.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
+
+    summary =  { 
+    "AXI-Stream Data Width": args.data_width,
+    "Configurator": "A 16 bit prescaler is used as an input to configure the baud rate for the UART."
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py

@@ -282,14 +282,44 @@ def main():
     json_group.add_argument("--json-template",  action="store_true",     help="Generate JSON Template")
 
     args = parser.parse_args()
+
+    details =  {   "IP details": {
+    'Name' : 'VexRiscv_CPU',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI',
+    'Description' : 'The VexRiscv CPU is a 32 bit, AXI4 compliant socomputations on FPGAs in the form of soft SoCs. It is a modern and complete soft processor that can be used to boot Operating Systems or used in a bare metal fashion.'}
+    }
 
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
 
+    summary =  { 
+    "AXI Data Width": "32",
+    "AXI ID Width": "1",
+    "CPU Mode Selected": args.variant,
+    }
+    # Calculate the value based on args.variant
+    if args.variant == "Cache_MMU_PLIC_CLINT":
+        cached_value = "  0x00000000-0xEFFFFFFF "
+        uncached_value = " >0xF0000000 "
+        interrupt = "PLIC and CLINT"
+    elif args.variant == "Cache_MMU":
+        cached_value = " 0x00000000-0xEFFFFFFF"
+        uncached_value = " >0xF0000000 "
+        interrupt = "Timers, External and Software"
+    else:
+        cached_value = " - "  # Provide a default value if needed
+        uncached_value = " Entire Range "
+        interrupt = "Timers, External and Software"
+    summary["Cached Region"] = cached_value
+    summary["Uncached Region"] = uncached_value
+    summary["Interrupt Type"] = interrupt
+
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")