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PLL generator parameters updated
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@bilalahmed-RS
bilalahmed-RS committed Oct 4, 2023
1 parent 5abe426 commit 4435ae4
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Showing 2 changed files with 129 additions and 28 deletions.
155 changes: 128 additions & 27 deletions rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,32 @@
logging.info(f'Log started at {timestamp}')

# Helpers ------------------------------------------------------------------------------------------

def freq_calc(self, fast_clk_freq, ref_clk_freq, c_range, d_range):
self.product = Signal()
self.ready = Signal()
a = fast_clk_freq
b = ref_clk_freq
c_range = 1000
d_range = 63
# Nested loop for iterating over c and d
for c in range(c_range):
for d in range(d_range):
# Calculate 2 * (a / b)
product_candidate = 2 * (a/ b)
print("product_candidate",product_candidate)
print(f" values found - C: {c}, D: {d}")
# Check if the candidate product matches the formula with c and d
print("candidate match", ((c+1) / (d+1)))
if product_candidate == ((c+1) / (d+1)):
# If a match is found, assign c, d, and the product to the respective signals
print(f"Matching values found - C: {c}, D: {d}")
pll_mult = c + 1
pll_div = d + 1
return pll_mult, pll_div
#break


class Open(Signal): pass

def colorer(s, color="bright"):
Expand Down Expand Up @@ -73,35 +99,110 @@ def __init__(self, platform, divided_clks, divide_clk_in_by_2, fast_clk_freq, re
self.GEARBOX_FAST_CLK = Signal()
self.LOCK = Signal()

pll_mult, pll_div = freq_calc(self, fast_clk_freq, ref_clk_freq, c_range=63, d_range=1000)
print("pll_mult", pll_mult , "pll_div", pll_div)

if divided_clks == 3:
if divided_clks == 4:
self.specials += Instance("PLL",
**kwargs,

p_DIVIDED_CLKS = Instance.PreformattedParam(divided_clks),
P_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2),
p_FAST_CLK_FREQ = Instance.PreformattedParam(fast_clk_freq),
p_REF_CLK_FREQ = Instance.PreformattedParam(ref_clk_freq),
p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div),
p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div),
p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div),
p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div),

i_PLL_EN = 1,
i_CLK_IN = self.CLK_IN,
i_CLK_OUT0_EN = self.CLK_OUT0_EN,
i_CLK_OUT1_EN = 0,
i_CLK_OUT2_EN = 0,
i_CLK_OUT3_EN = 0,
o_CLK_OUT0 = self.CLK_OUT0,
o_CLK_OUT1 = self.CLK_OUT1,
o_CLK_OUT2 = self.CLK_OUT2,
o_CLK_OUT3 = self.CLK_OUT3,
o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK,
o_LOCK = self.LOCK
)

self.add_sources(platform)
**kwargs,
p_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2),
p_PLL_MULT = Instance.PreformattedParam(pll_mult),
p_PLL_DIV = Instance.PreformattedParam(pll_div),
p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div),
p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div),
p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div),
p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div),

i_PLL_EN = 1,
i_CLK_IN = self.CLK_IN,
i_CLK_OUT0_EN = 1,
i_CLK_OUT1_EN = 1,
i_CLK_OUT2_EN = 1,
i_CLK_OUT3_EN = 1,
o_CLK_OUT0 = self.CLK_OUT0,
o_CLK_OUT1 = self.CLK_OUT1,
o_CLK_OUT2 = self.CLK_OUT2,
o_CLK_OUT3 = self.CLK_OUT3,
o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK,
o_LOCK = self.LOCK
)
elif divided_clks == 3:
self.specials += Instance("PLL",
**kwargs,
p_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2),
p_PLL_MULT = Instance.PreformattedParam(pll_mult),
p_PLL_DIV = Instance.PreformattedParam(pll_div),
p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div),
p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div),
p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div),
p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div),

i_PLL_EN = 1,
i_CLK_IN = self.CLK_IN,
i_CLK_OUT0_EN = 1,
i_CLK_OUT1_EN = 1,
i_CLK_OUT2_EN = 1,
i_CLK_OUT3_EN = 0,
o_CLK_OUT0 = self.CLK_OUT0,
o_CLK_OUT1 = self.CLK_OUT1,
o_CLK_OUT2 = self.CLK_OUT2,
# o_CLK_OUT3 = self.CLK_OUT3,
o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK,
o_LOCK = self.LOCK
)

elif divided_clks == 2:
self.specials += Instance("PLL",
**kwargs,
p_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2),
p_PLL_MULT = Instance.PreformattedParam(pll_mult),
p_PLL_DIV = Instance.PreformattedParam(pll_div),
p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div),
p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div),
p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div),
p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div),

i_PLL_EN = 1,
i_CLK_IN = self.CLK_IN,
i_CLK_OUT0_EN = 1,
i_CLK_OUT1_EN = 1,
i_CLK_OUT2_EN = 0,
i_CLK_OUT3_EN = 0,
o_CLK_OUT0 = self.CLK_OUT0,
o_CLK_OUT1 = self.CLK_OUT1,
# o_CLK_OUT2 = self.CLK_OUT2,
# o_CLK_OUT3 = self.CLK_OUT3,
o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK,
o_LOCK = self.LOCK
)

elif divided_clks == 1:
self.specials += Instance("PLL",
**kwargs,
p_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2),
p_PLL_MULT = Instance.PreformattedParam(pll_mult),
p_PLL_DIV = Instance.PreformattedParam(pll_div),
p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div),
p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div),
p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div),
p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div),

i_PLL_EN = 1,
i_CLK_IN = self.CLK_IN,
i_CLK_OUT0_EN = 1,
i_CLK_OUT1_EN = 0,
i_CLK_OUT2_EN = 0,
i_CLK_OUT3_EN = 0,
o_CLK_OUT0 = self.CLK_OUT0,
# o_CLK_OUT1 = self.CLK_OUT1,
# o_CLK_OUT2 = self.CLK_OUT2,
# o_CLK_OUT3 = self.CLK_OUT3,
o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK,
o_LOCK = self.LOCK
)


self.add_sources(platform)

@staticmethod
def add_sources(platform):
Expand Down
2 changes: 1 addition & 1 deletion rapidsilicon/ip/pll/v1_0/pll_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -171,7 +171,7 @@ def main():
clk_out1_div=args.clk_out1_div,
clk_out2_div=args.clk_out2_div,
clk_out3_div=args.clk_out3_div)
a

# Build Project --------------------------------------------------------------------------------
if args.build:
rs_builder.prepare(
Expand Down

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