Merge pull request #173 from RapidSilicon/new_parameters

New parameters
os-fpga · Sep 19, 2023 · 022b280 · 022b280
2 parents 760dadc + 8dee227
commit 022b280
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diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py b/rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py
@@ -9,6 +9,8 @@
 import logging
 import argparse
 
+from datetime import datetime
+
 from litex_wrapper.ahb2axi_bridge_litex_wrapper import AHB2AXI4
 
 from migen import *
@@ -164,6 +166,39 @@ def main():
             platform   = platform,
             module     = module,
         )
+
+        # IP_ID Parameter
+        now = datetime.now()
+        my_year         = now.year - 2022
+        year            = (bin(my_year)[2:]).zfill(7) # 7-bits  # Removing '0b' prefix = [2:]
+        month           = (bin(now.month)[2:]).zfill(4) # 4-bits
+        day             = (bin(now.day)[2:]).zfill(5) # 5-bits
+        mod_hour        = now.hour % 12 # 12 hours Format
+        hour            = (bin(mod_hour)[2:]).zfill(4) # 4-bits
+        minute          = (bin(now.minute)[2:]).zfill(6) # 6-bits
+        second          = (bin(now.second)[2:]).zfill(6) # 6-bits
+
+        # Concatenation for IP_ID Parameter
+        ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
+        ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])
+
+        # IP_VERSION parameter
+        #               Base  _  Major _ Minor
+        ip_version = "00000000_00000000_0000000000000001"
+        ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])
+
+        wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "ahb2axi_bridge", "v1_0", args.build_name, "src",args.build_name+".v")
+        new_lines = []
+        with open (wrapper, "r") as file:
+            lines = file.readlines()
+            for i, line in enumerate(lines):
+                if ("module {}".format(args.build_name)) in line:
+                    new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"AHB2AXI\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
+                else:
+                    new_lines.append(line)
+
+        with open(os.path.join(wrapper), "w") as file:
+            file.writelines(new_lines)
 
 if __name__ == "__main__":
     main()
diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py b/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py
@@ -68,6 +68,10 @@ def __init__(self, platform, m_axi):
         self.specials += Instance("ahb2axi4",
             # Parameters.
             # -----------
+            # IP Parameters
+            p_IP_TYPE           = Instance.PreformattedParam("IP_TYPE"),
+            p_IP_ID             = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION        = Instance.PreformattedParam("IP_VERSION"),
             # Global AXI
             p_data_width        = Instance.PreformattedParam(data_width),
             p_addr_width        = Instance.PreformattedParam(address_width),

diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/src/ahb2axi4.sv b/rapidsilicon/ip/ahb2axi_bridge/v1_0/src/ahb2axi4.sv
@@ -36,9 +36,12 @@
 
 
 module ahb2axi4 #(
-parameter id_width	        = 1,
-parameter addr_width     = 32,
-parameter data_width        = 32
+  parameter IP_TYPE 		= "AHB2AXI",
+	parameter IP_VERSION 	= 32'h1, 
+	parameter IP_ID 		  = 32'h2591324,
+parameter id_width	    = 1,
+parameter addr_width    = 32,
+parameter data_width    = 32
 ) 
 
 

diff --git a/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py b/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py
@@ -9,6 +9,8 @@
 import logging
 import argparse
 
+from datetime import datetime
+
 from litex_wrapper.axi2axilite_bridge_litex_wrapper import AXI2AXILITE
 
 from migen import *
@@ -129,6 +131,39 @@ def main():
             platform   = platform,
             module     = module,
         )
+
+        # IP_ID Parameter
+        now = datetime.now()
+        my_year         = now.year - 2022
+        year            = (bin(my_year)[2:]).zfill(7) # 7-bits  # Removing '0b' prefix = [2:]
+        month           = (bin(now.month)[2:]).zfill(4) # 4-bits
+        day             = (bin(now.day)[2:]).zfill(5) # 5-bits
+        mod_hour        = now.hour % 12 # 12 hours Format
+        hour            = (bin(mod_hour)[2:]).zfill(4) # 4-bits
+        minute          = (bin(now.minute)[2:]).zfill(6) # 6-bits
+        second          = (bin(now.second)[2:]).zfill(6) # 6-bits
+
+        # Concatenation for IP_ID Parameter
+        ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
+        ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])
+
+        # IP_VERSION parameter
+        #               Base  _  Major _ Minor
+        ip_version = "00000000_00000000_0000000000000001"
+        ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])
+
+        wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axi2axilite_bridge", "v1_0", args.build_name, "src",args.build_name+".v")
+        new_lines = []
+        with open (wrapper, "r") as file:
+            lines = file.readlines()
+            for i, line in enumerate(lines):
+                if ("module {}".format(args.build_name)) in line:
+                    new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"AXI2AXIL\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
+                else:
+                    new_lines.append(line)
+
+        with open(os.path.join(wrapper), "w") as file:
+            file.writelines(new_lines)
 
 if __name__ == "__main__":
     main()
diff --git a/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py b/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py
@@ -52,6 +52,11 @@ def __init__(self, platform, s_axi, m_axi):
         self.specials += Instance("axi2axilite",
             # Parameters.
             # -----------
+            # IP Parameters
+            p_IP_TYPE               = Instance.PreformattedParam("IP_TYPE"),
+            p_IP_ID                 = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION            = Instance.PreformattedParam("IP_VERSION"),
+
             # Global AXI
             p_C_AXI_DATA_WIDTH      = Instance.PreformattedParam(data_width),
             p_C_AXI_ADDR_WIDTH      = Instance.PreformattedParam(address_width),

diff --git a/rapidsilicon/ip/axi2axilite_bridge/v1_0/src/axi2axilite.v b/rapidsilicon/ip/axi2axilite_bridge/v1_0/src/axi2axilite.v
@@ -51,19 +51,22 @@
 `default_nettype	none
 // }}}
 module axi2axilite #(
-		// {{{
-		parameter integer C_AXI_ID_WIDTH	= 2,
-		parameter integer C_AXI_DATA_WIDTH	= 32,
-		parameter integer C_AXI_ADDR_WIDTH	= 6,
-		parameter	 [0:0]	OPT_WRITES	= 1,
-		parameter	 [0:0]	OPT_READS	= 1,
-		parameter	 [0:0]	OPT_LOWPOWER    = 0,
-		// Log (based two) of the maximum number of outstanding AXI
-		// (not AXI-lite) transactions.  If you multiply 2^LGFIFO * 256,
-		// you'll get the maximum number of outstanding AXI-lite
-		// transactions
-		parameter	LGFIFO			= 4
-		// }}}
+	parameter IP_TYPE 					= "AXI2AXIL",
+	parameter IP_VERSION 				= 32'h1, 
+	parameter IP_ID 					= 32'h2591529,
+	// {{{
+	parameter integer C_AXI_ID_WIDTH	= 2,
+	parameter integer C_AXI_DATA_WIDTH	= 32,
+	parameter integer C_AXI_ADDR_WIDTH	= 6,
+	parameter	 [0:0]	OPT_WRITES		= 1,
+	parameter	 [0:0]	OPT_READS		= 1,
+	parameter	 [0:0]	OPT_LOWPOWER    = 0,
+	// Log (based two) of the maximum number of outstanding AXI
+	// (not AXI-lite) transactions.  If you multiply 2^LGFIFO * 256,
+	// you'll get the maximum number of outstanding AXI-lite
+	// transactions
+	parameter	LGFIFO					= 4
+	// }}}
 	) (
 		// {{{
 		input	wire								S_AXI_ACLK,

diff --git a/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py b/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py
@@ -11,6 +11,8 @@
 import argparse
 import math
 
+from datetime import datetime
+
 from litex_wrapper.axi_async_fifo_litex_wrapper import AXIASYNCFIFO
 
 from migen import *
@@ -150,6 +152,39 @@ def main():
             platform   = platform,
             module     = module,
         )
+
+        # IP_ID Parameter
+        now = datetime.now()
+        my_year         = now.year - 2022
+        year            = (bin(my_year)[2:]).zfill(7) # 7-bits  # Removing '0b' prefix = [2:]
+        month           = (bin(now.month)[2:]).zfill(4) # 4-bits
+        day             = (bin(now.day)[2:]).zfill(5) # 5-bits
+        mod_hour        = now.hour % 12 # 12 hours Format
+        hour            = (bin(mod_hour)[2:]).zfill(4) # 4-bits
+        minute          = (bin(now.minute)[2:]).zfill(6) # 6-bits
+        second          = (bin(now.second)[2:]).zfill(6) # 6-bits
+
+        # Concatenation for IP_ID Parameter
+        ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
+        ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])
+
+        # IP_VERSION parameter
+        #               Base  _  Major _ Minor
+        ip_version = "00000000_00000000_0000000000000001"
+        ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])
+
+        wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axi_async_fifo", "v1_0", args.build_name, "src",args.build_name+".v")
+        new_lines = []
+        with open (wrapper, "r") as file:
+            lines = file.readlines()
+            for i, line in enumerate(lines):
+                if ("module {}".format(args.build_name)) in line:
+                    new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"ASYNCFFO\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
+                else:
+                    new_lines.append(line)
+
+        with open(os.path.join(wrapper), "w") as file:
+            file.writelines(new_lines)
 
 if __name__ == "__main__":
     main()
diff --git a/rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py b/rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py
@@ -60,6 +60,10 @@ def __init__(self, platform, s_axi, m_axi, fifo_depth):
         self.specials += Instance("axi_async_fifo",
             # Parameters.
             # -----------
+            # IP Parameters
+            p_IP_TYPE           = Instance.PreformattedParam("IP_TYPE"),
+            p_IP_ID             = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION        = Instance.PreformattedParam("IP_VERSION"),
             # Global.
             p_AXI_DATA_WIDTH        = data_width,
             p_AXI_ADDR_WIDTH        = addr_width,

diff --git a/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py b/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py
@@ -9,6 +9,8 @@
 import logging
 import argparse
 
+from datetime import datetime
+
 from litex_wrapper.axi_cdma_litex_wrapper import AXICDMA
 
 from migen import *
@@ -178,6 +180,39 @@ def main():
             platform   = platform,
             module     = module,
         )
+
+        # IP_ID Parameter
+        now = datetime.now()
+        my_year         = now.year - 2022
+        year            = (bin(my_year)[2:]).zfill(7) # 7-bits  # Removing '0b' prefix = [2:]
+        month           = (bin(now.month)[2:]).zfill(4) # 4-bits
+        day             = (bin(now.day)[2:]).zfill(5) # 5-bits
+        mod_hour        = now.hour % 12 # 12 hours Format
+        hour            = (bin(mod_hour)[2:]).zfill(4) # 4-bits
+        minute          = (bin(now.minute)[2:]).zfill(6) # 6-bits
+        second          = (bin(now.second)[2:]).zfill(6) # 6-bits
+
+        # Concatenation for IP_ID Parameter
+        ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
+        ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])
+
+        # IP_VERSION parameter
+        #               Base  _  Major _ Minor
+        ip_version = "00000000_00000000_0000000000000001"
+        ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])
+
+        wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axi_cdma", "v1_0", args.build_name, "src",args.build_name+".v")
+        new_lines = []
+        with open (wrapper, "r") as file:
+            lines = file.readlines()
+            for i, line in enumerate(lines):
+                if ("module {}".format(args.build_name)) in line:
+                    new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"CDMA1\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
+                else:
+                    new_lines.append(line)
+
+        with open(os.path.join(wrapper), "w") as file:
+            file.writelines(new_lines)
 
 if __name__ == "__main__":
     main()
diff --git a/rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py b/rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py
@@ -79,6 +79,10 @@ def __init__(self, platform, m_axi,
         self.specials += Instance("axi_cdma",
             # Parameters.
             # -----------
+            # IP Parameters
+            p_IP_TYPE                   = Instance.PreformattedParam("IP_TYPE"),
+            p_IP_ID                     = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION                = Instance.PreformattedParam("IP_VERSION"),
             # Global AXI
             p_AXI_DATA_WIDTH            = Instance.PreformattedParam(data_width),
             p_AXI_ADDR_WIDTH            = Instance.PreformattedParam(address_width),

diff --git a/rapidsilicon/ip/axi_cdma/v1_0/src/axi_cdma.v b/rapidsilicon/ip/axi_cdma/v1_0/src/axi_cdma.v
@@ -33,6 +33,10 @@ THE SOFTWARE.
  */
 module axi_cdma #
 (
+    parameter IP_TYPE 		= "CDMA1",
+	parameter IP_VERSION 	= 32'h1, 
+	parameter IP_ID 		= 32'h2591446,
+
     // Width of data bus in bits
     parameter AXI_DATA_WIDTH = 32,
     // Width of address bus in bits

diff --git a/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py b/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py
@@ -9,6 +9,8 @@
 import logging
 import argparse
 
+from datetime import datetime
+
 from litex_wrapper.axi_cdma_litex_wrapper import AXICDMA
 
 from migen import *
@@ -136,6 +138,39 @@ def main():
             platform   = platform,
             module     = module,
         )
+
+        # IP_ID Parameter
+        now = datetime.now()
+        my_year         = now.year - 2022
+        year            = (bin(my_year)[2:]).zfill(7) # 7-bits  # Removing '0b' prefix = [2:]
+        month           = (bin(now.month)[2:]).zfill(4) # 4-bits
+        day             = (bin(now.day)[2:]).zfill(5) # 5-bits
+        mod_hour        = now.hour % 12 # 12 hours Format
+        hour            = (bin(mod_hour)[2:]).zfill(4) # 4-bits
+        minute          = (bin(now.minute)[2:]).zfill(6) # 6-bits
+        second          = (bin(now.second)[2:]).zfill(6) # 6-bits
+
+        # Concatenation for IP_ID Parameter
+        ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
+        ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])
+
+        # IP_VERSION parameter
+        #               Base  _  Major _ Minor
+        ip_version = "00000000_00000000_0000000000000001"
+        ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])
+
+        wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axi_cdma", "v2_0", args.build_name, "src",args.build_name+".v")
+        new_lines = []
+        with open (wrapper, "r") as file:
+            lines = file.readlines()
+            for i, line in enumerate(lines):
+                if ("module {}".format(args.build_name)) in line:
+                    new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"CDMA2\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
+                else:
+                    new_lines.append(line)
+
+        with open(os.path.join(wrapper), "w") as file:
+            file.writelines(new_lines)
 
 if __name__ == "__main__":
     main()
diff --git a/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py b/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py
@@ -58,6 +58,10 @@ def __init__(self, platform, axi, axil):
         self.specials += Instance("axi_cdma",
             # Parameters.
             # -----------
+            # IP Parameters
+            p_IP_TYPE                   = Instance.PreformattedParam("IP_TYPE"),
+            p_IP_ID                     = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION                = Instance.PreformattedParam("IP_VERSION"),
             # Global AXI
             p_C_AXI_DATA_WIDTH          = (m_data_width),
             p_C_AXI_ADDR_WIDTH          = (m_address_width),

diff --git a/rapidsilicon/ip/axi_cdma/v2_0/src/axi_cdma.v b/rapidsilicon/ip/axi_cdma/v2_0/src/axi_cdma.v
@@ -64,6 +64,9 @@
 // `define			AXI3
 // }}}
 module	axi_cdma #(
+		parameter IP_TYPE 		= "CDMA2",
+		parameter IP_VERSION 	= 32'h1, 
+		parameter IP_ID 		= 32'h2591451,
 		// {{{
 		parameter	C_AXI_ID_WIDTH = 1,
 		parameter	C_AXI_ADDR_WIDTH = 32,