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module/icp/asm-arm/sha2: enable non-SIMD asm kernels on armv5/6 #15623

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Dec 5, 2023
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module/icp/asm-arm/sha2: enable non-SIMD asm kernels on armv5/6 #15623

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22 changes: 13 additions & 9 deletions module/icp/algs/sha2/sha256_impl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,15 @@ const sha256_ops_t sha256_shani_impl = {
};
#endif

#elif defined(__aarch64__) || (defined(__arm__) && __ARM_ARCH > 6)
#elif defined(__aarch64__) || defined(__arm__)
extern void zfs_sha256_block_armv7(uint32_t s[8], const void *, size_t);
const sha256_ops_t sha256_armv7_impl = {
.is_supported = sha2_is_supported,
.transform = zfs_sha256_block_armv7,
.name = "armv7"
};

#if __ARM_ARCH > 6
static boolean_t sha256_have_neon(void)
{
return (kfpu_allowed() && zfs_neon_available());
Expand All @@ -129,13 +137,6 @@ static boolean_t sha256_have_armv8ce(void)
return (kfpu_allowed() && zfs_sha256_available());
}

extern void zfs_sha256_block_armv7(uint32_t s[8], const void *, size_t);
const sha256_ops_t sha256_armv7_impl = {
.is_supported = sha2_is_supported,
.transform = zfs_sha256_block_armv7,
.name = "armv7"
};

TF(zfs_sha256_block_neon, tf_sha256_neon);
const sha256_ops_t sha256_neon_impl = {
.is_supported = sha256_have_neon,
Expand All @@ -149,6 +150,7 @@ const sha256_ops_t sha256_armv8_impl = {
.transform = tf_sha256_armv8ce,
.name = "armv8-ce"
};
#endif

#elif defined(__PPC64__)
static boolean_t sha256_have_isa207(void)
Expand Down Expand Up @@ -192,11 +194,13 @@ static const sha256_ops_t *const sha256_impls[] = {
#if defined(__x86_64) && defined(HAVE_SSE4_1)
&sha256_shani_impl,
#endif
#if defined(__aarch64__) || (defined(__arm__) && __ARM_ARCH > 6)
#if defined(__aarch64__) || defined(__arm__)
&sha256_armv7_impl,
#if __ARM_ARCH > 6
&sha256_neon_impl,
&sha256_armv8_impl,
#endif
#endif
#if defined(__PPC64__)
&sha256_ppc_impl,
&sha256_power8_impl,
Expand Down
19 changes: 8 additions & 11 deletions module/icp/algs/sha2/sha512_impl.c
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Expand Up @@ -88,14 +88,15 @@ const sha512_ops_t sha512_avx2_impl = {
};
#endif

#elif defined(__aarch64__)
#elif defined(__aarch64__) || defined(__arm__)
extern void zfs_sha512_block_armv7(uint64_t s[8], const void *, size_t);
const sha512_ops_t sha512_armv7_impl = {
.is_supported = sha2_is_supported,
.transform = zfs_sha512_block_armv7,
.name = "armv7"
};

#if defined(__aarch64__)
static boolean_t sha512_have_armv8ce(void)
{
return (kfpu_allowed() && zfs_sha512_available());
Expand All @@ -107,15 +108,9 @@ const sha512_ops_t sha512_armv8_impl = {
.transform = tf_sha512_armv8ce,
.name = "armv8-ce"
};
#endif

#elif defined(__arm__) && __ARM_ARCH > 6
extern void zfs_sha512_block_armv7(uint64_t s[8], const void *, size_t);
const sha512_ops_t sha512_armv7_impl = {
.is_supported = sha2_is_supported,
.transform = zfs_sha512_block_armv7,
.name = "armv7"
};

#if defined(__arm__) && __ARM_ARCH > 6
static boolean_t sha512_have_neon(void)
{
return (kfpu_allowed() && zfs_neon_available());
Expand All @@ -127,6 +122,7 @@ const sha512_ops_t sha512_neon_impl = {
.transform = tf_sha512_neon,
.name = "neon"
};
#endif

#elif defined(__PPC64__)
TF(zfs_sha512_ppc, tf_sha512_ppc);
Expand Down Expand Up @@ -164,14 +160,15 @@ static const sha512_ops_t *const sha512_impls[] = {
#if defined(__x86_64) && defined(HAVE_AVX2)
&sha512_avx2_impl,
#endif
#if defined(__aarch64__)
#if defined(__aarch64__) || defined(__arm__)
&sha512_armv7_impl,
#if defined(__aarch64__)
&sha512_armv8_impl,
#endif
#if defined(__arm__) && __ARM_ARCH > 6
&sha512_armv7_impl,
&sha512_neon_impl,
#endif
#endif
#if defined(__PPC64__)
&sha512_ppc_impl,
&sha512_power8_impl,
Expand Down
8 changes: 3 additions & 5 deletions module/icp/asm-arm/sha2/sha256-armv7.S
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Original file line number Diff line number Diff line change
Expand Up @@ -1837,6 +1837,7 @@ zfs_sha256_block_armv7:
#endif
.size zfs_sha256_block_armv7,.-zfs_sha256_block_armv7

#if __ARM_ARCH__ >= 7
.arch armv7-a
.fpu neon

Expand All @@ -1849,11 +1850,7 @@ zfs_sha256_block_neon:
stmdb sp!,{r4-r12,lr}

sub r11,sp,#16*4+16
#if __ARM_ARCH__ >=7
adr r14,K256
#else
ldr r14,=K256
#endif
bic r11,r11,#15 @ align for 128-bit stores
mov r12,sp
mov sp,r11 @ alloca
Expand Down Expand Up @@ -2773,4 +2770,5 @@ zfs_sha256_block_armv8:
bx lr @ bx lr
.size zfs_sha256_block_armv8,.-zfs_sha256_block_armv8

#endif
#endif // #if __ARM_ARCH__ >= 7
#endif // #if defined(__arm__)
4 changes: 3 additions & 1 deletion module/icp/asm-arm/sha2/sha512-armv7.S
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Expand Up @@ -493,6 +493,7 @@ zfs_sha512_block_armv7:
#endif
.size zfs_sha512_block_armv7,.-zfs_sha512_block_armv7

#if __ARM_ARCH__ >= 7
.arch armv7-a
.fpu neon

Expand Down Expand Up @@ -1822,4 +1823,5 @@ zfs_sha512_block_neon:
VFP_ABI_POP
bx lr @ .word 0xe12fff1e
.size zfs_sha512_block_neon,.-zfs_sha512_block_neon
#endif
#endif // #if __ARM_ARCH__ >= 7
#endif // #if defined(__arm__)