assertion failed for bresp

[dvusingh]

Hi,

I tried to run the benchmarck median test with cv32_imac_sv32 configurantion file.

The test is finished sucessfully and all the instructions are matched.But in the log file I found one violation related to bresp_all_done assertions shown below.

$finish called from file "/tools/synopsys/vcs/T-2022.06-SP1-1/etc/uvm-1.2/base/uvm_root.svh", line 527.
"/cva6/verif/core-v-verif/lib/uvm_agents/uvma_axi5/src/uvma_axi_assert.sv", 142: uvmt_cva6_tb.cva6_dut_wrap.axi_assert.axi_mix_assert.unnamed$$_0.axi4_bresp_all_done: started at 43599500ps failed at 43599500ps
Offending '(burst_resp[i] == 0)'
UVM_ERROR @ 43599.500 ns : uvma_axi_assert.sv(144) reporter [AXI4 protocol checks assertion] Violation of bresp_all_done
UVM_INFO @ 43599.500 ns : uvma_axi_assert.sv(336) reporter [AXI4 protocol checks assertion] coverage cov_w_data_num property = 441
UVM_INFO @ 43599.500 ns : uvma_axi_assert.sv(337) reporter [AXI4 protocol checks assertion] coverage cov_w_data_num_not property = 0
UVM_INFO @ 43599.500 ns : uvma_axi_assert.sv(338) reporter [AXI4 protocol checks assertion] coverage cov_errm_wstrb property = 1764
UVM_INFO @ 43599.500 ns : uvma_axi_assert.sv(339) reporter [AXI4 protocol checks assertion] coverage r_last property = 0
UVM_INFO @ 43599.500 ns : uvma_axi_assert.sv(340) reporter [AXI4 protocol checks assertion] coverage axi4_errs_rid property = 0
UVM_INFO @ 43599.500 ns : uvma_axi_assert.sv(341) reporter [AXI4 protocol checks assertion] coverage burst_ter_early property = 0

uvmt_cva6_tb.end_of_test: *** Test Summary ***

FFFFFFFF   AAAAAA   IIIIII  LL        EEEEEEEE  DDDDDDD       
FF        AA    AA    II    LL        EE        DD    DD      
FF        AA    AA    II    LL        EE        DD    DD      
FFFFF     AAAAAAAA    II    LL        EEEEE     DD    DD      
FF        AA    AA    II    LL        EE        DD    DD      
FF        AA    AA    II    LL        EE        DD    DD      
FF        AA    AA  IIIIII  LLLLLLLL  EEEEEEEE  DDDDDDD       
----------------------------------------------------------
                   SIMULATION FAILED                    
             test exit code = 0 (0x00000000)
----------------------------------------------------------

$finish at simulation time 43599.500 ns

From the waveform I found that there is write request initiated at time 43596.5ns , but the simulation finished at time 434599.5 ns without getting bresp signals.

I tried to increased the simulation time , but still the test is finished at 43599.5 ns without getting the bresp signal from axi-interconnect.

How to resolve this issue?

Thanks

[JeanRochCoulon]

With @AEzzejjari We are fixing this issue.

[dvusingh]

Please let me know once the issue is fixed.

Thanks

[github-actions]

👋 Hi there!

This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊

[github-actions]

👋 Hi there!

This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊

[JeanRochCoulon]

The issue should be fixed. Please tell me if it is the case on your side.