Welcome to CVA6 Discussions!

[zarubaf]

👋 Welcome!

We’re using Discussions as a place to connect with other members of our community. We hope that you:

• Ask questions you’re wondering about.
• Share ideas.
• Engage with other community members.
• Welcome others and are open-minded. Remember that this is a community we
  build together 💪.

To get started, comment below with an introduction of yourself and tell us about what you do with this community.

[aleemrehaman]

Hi Zaruba , I would like to explore more.. how do I connect with you?

…

On Mon, 14 Dec 2020 at 2:43 PM, Florian Zaruba ***@***.***> wrote: 👋 Welcome! We’re using Discussions as a place to connect with other members of our community. We hope that you: - Ask questions you’re wondering about. - Share ideas. - Engage with other community members. - Welcome others and are open-minded. Remember that this is a community we build together 💪. To get started, comment below with an introduction of yourself and tell us about what you do with this community. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#572>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AIWAKIJINAGNBBRGKQTGMTLSUXJKRANCNFSM4U2NRMMA> .

[zarubaf]

Welcome, @aleemrehaman!

Please feel free to open a new question if you have a particular question or an issue if you encounter any problems with CVA6.

In case you are interested in joining OpenHW Group (and the respective task groups) please find more information on our website. You can also find past talks there in case you want to get a broader overview.

You can also connect to me using our OpenHW Group Mattermost!

I hope that helps!

Best,
Florian

[coreLover0019]

Hi, zarubaf,

I am learning "openpiton + cva6" recently, and I learned about that wt_cache_subsystem is designed for openpiton.

I checked the rtl code, but I didn't find a mechanism/channel that L1.5/L2 send 'invalidation' msg to L1D.

If core1 writes position X, and the core0's L1D has a valid cached data whose address is also X, then,
core0's L1D should receive a cache line invalidation msg, but I didn't see the corresponding code in wt_cache_subsystem.

Would you please spend several time for answering my question ?
Thanks a lot

[bufans]

Hi，zarubaf

Does the issue stage need to be stall after issued one control flow instruction? I saw the issue stage has one input port named resolve_brach_i, but it is unused.

[FranDuqueAyachi]

Hi! I have finished following all the steps found in the git repository. I have managed to simulate the core cva6 with the C program "hello world". I would like to know if it is possible to interpret the most important signals when simulating this program, because I can't see reflected the decisions that are in the cva6 documentation, for example:

Some jump prediction.
the communication between the Fetch stage and the MMU.
Decoding of the instruction.
See how the scoreboard sends the instructions to the different FU.

I would be very grateful if someone could help me to interpret the results of the simulation because there are a lot of signals and I can not transform all this information into the ideas that cva6 raises.