Add simple formatting tool in addition to syntactic and semantic linter

onera · Dec 13, 2024 · 7fe575a · 7fe575a
1 parent f1933c1
commit 7fe575a
Show file tree

Hide file tree

Showing 187 changed files with 12,807 additions and 8,838 deletions.
diff --git a/.scalafmt.conf b/.scalafmt.conf
@@ -0,0 +1,2 @@
+version = 3.8.4-RC3
+runner.dialect = scala32
diff --git a/build.sbt b/build.sbt
@@ -102,6 +102,7 @@ lazy val commonSettings = Seq(
   sbtVersion := "1.8.2",
   scalafixOnCompile := true,
   semanticdbEnabled := true,
+  scalafmtOnCompile := true,
   scalafixDependencies += "io.github.dedis" %% "scapegoat-scalafix" % "1.1.4",
   semanticdbVersion := scalafixSemanticdb.revision,
     scalacOptions := Seq("-unchecked", "-deprecation", "-feature", "-Werror"),

diff --git a/project/plugins.sbt b/project/plugins.sbt
@@ -3,3 +3,4 @@ addSbtPlugin("se.marcuslonnberg" % "sbt-docker" % "1.9.0")
 addSbtPlugin("org.xerial.sbt" % "sbt-sonatype" % "2.3")
 addSbtPlugin("com.github.sbt" % "sbt-pgp" % "2.2.1")
 addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.12.1")
+addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.6")
diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcPlatform.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcPlatform.scala
@@ -1,123 +1,134 @@
-/*******************************************************************************
- * Copyright (c)  2023. ONERA
- * This file is part of PML Analyzer
- *
- * PML Analyzer is free software ;
- * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation ;
- * either version 2 of  the License, or (at your option) any later version.
- *
- * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License along with this program ;
- *  if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307  USA
- ******************************************************************************/
+/** *****************************************************************************
+  * Copyright (c) 2023. ONERA This file is part of PML Analyzer
+  *
+  * PML Analyzer is free software ; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published by the
+  * Free Software Foundation ; either version 2 of the License, or (at your
+  * option) any later version.
+  *
+  * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT
+  * ANY WARRANTY ; without even the implied warranty of MERCHANTABILITY or
+  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+  * for more details.
+  *
+  * You should have received a copy of the GNU Lesser General Public License
+  * along with this program ; if not, write to the Free Software Foundation,
+  * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+  */
 
 package onera.pmlanalyzer.pml.examples.mySys
 
 import onera.pmlanalyzer.pml.model.hardware.*
 import onera.pmlanalyzer.pml.operators.*
 import sourcecode.Name
 
-/**
-  * Simple model of the Keystone platform illustrating the main features of PML.
-  * The components of the architectures can be created using the constructors provided in [[pml.model.hardware.BaseHardwareNodeBuilder]]
-  * For instance the [[package.SimpleKeystonePlatform.dma]] is built with:
-  * {{{val dma: Initiator = Initiator()}}}
-  * An axi-bus is built with:
-  * {{{val axi-bus: SimpleTransporter= SimpleTransporter()}}}
-  * A peripheral or a memory is built with
-  * {{{val sram: Target = Target()}}}
-  * Some components may be composite, if you want to define one instance of composite you can use the object
-  * instantiation pattern used for the TeraNet
-  * {{{object TeraNet extends Composite }}}
-  * You can also define a type of Composite that may be instantiated afterward, for instance here ARMCores are defined
-  * as a composition of a core (initiator) and a cache (transporter). A name is given as a parameter of the ARMCore class
-  * {{{class ARMCore (name:Symbol) extends Composite }}}
-  * Then components can be linked together, this operation simply connect the service of the same type provided by the
-  * two components. For instance
-  * {{{ARM0.core link axi_bus}}}
-  * links the [[pml.model.service.Load]] and [[pml.model.service.Store]] service of the ARM0.core to the ones of the axi-bus
-  * Beware that all links are not possible, for instance you cannot link two [[pml.model.hardware.Target]] or a
-  * [[pml.model.hardware.Composite]] to another component.
-  * @see [[pml.operators.Link.Ops]] for link operator definition
-  * @see [[pml.model.hardware.BaseHardwareNodeBuilder]] for component instantiation
-  * @param name the name of the final object merging all facets of the model
-  *
+/** Simple model of the Keystone platform illustrating the main features of PML.
+  * The components of the architectures can be created using the constructors
+  * provided in [[pml.model.hardware.BaseHardwareNodeBuilder]] For instance the
+  * [[package.SimpleKeystonePlatform.dma]] is built with:
+  * {{{val dma: Initiator = Initiator()}}} An axi-bus is built with:
+  * {{{val axi-bus: SimpleTransporter= SimpleTransporter()}}} A peripheral or a
+  * memory is built with {{{val sram: Target = Target()}}} Some components may
+  * be composite, if you want to define one instance of composite you can use
+  * the object instantiation pattern used for the TeraNet
+  * {{{object TeraNet extends Composite}}} You can also define a type of
+  * Composite that may be instantiated afterward, for instance here ARMCores are
+  * defined as a composition of a core (initiator) and a cache (transporter). A
+  * name is given as a parameter of the ARMCore class
+  * {{{class ARMCore (name:Symbol) extends Composite}}} Then components can be
+  * linked together, this operation simply connect the service of the same type
+  * provided by the two components. For instance {{{ARM0.core link axi_bus}}}
+  * links the [[pml.model.service.Load]] and [[pml.model.service.Store]] service
+  * of the ARM0.core to the ones of the axi-bus Beware that all links are not
+  * possible, for instance you cannot link two [[pml.model.hardware.Target]] or
+  * a [[pml.model.hardware.Composite]] to another component.
+  * @see
+  *   [[pml.operators.Link.Ops]] for link operator definition
+  * @see
+  *   [[pml.model.hardware.BaseHardwareNodeBuilder]] for component instantiation
+  * @param name
+  *   the name of the final object merging all facets of the model
   */
 class MyProcPlatform(name: Symbol) extends Platform(name) {
 
-  /**
-    * Enable to provide the name implicitly
-    * @param implicitName the name of the object/class inheriting from this class
-    *                     will be the name of platform
+  /** Enable to provide the name implicitly
+    * @param implicitName
+    *   the name of the object/class inheriting from this class will be the name
+    *   of platform
     */
   def this()(implicit implicitName: Name) = {
     this(Symbol(implicitName.value))
   }
 
-  /**  Initiator modelling the DMA 
+  /** Initiator modelling the DMA
     * @group initiator
     */
   val dma: Initiator = Initiator()
 
-  /** Composite modelling the Teranet 
+  /** Composite modelling the Teranet
     * @group composite
     */
   object TeraNet extends Composite {
+
     /** Transporter modelling the peripheral interconnect
-      * @group transporter */
+      * @group transporter
+      */
     val periph_bus: SimpleTransporter = SimpleTransporter()
 
     /** Transporter modelling the register interconnect
-      * @group transporter */
+      * @group transporter
+      */
     val config_bus: SimpleTransporter = SimpleTransporter()
 
     periph_bus link config_bus
   }
 
-  /** Composite modelling memory subsystem 
-    * @group composite */
+  /** Composite modelling memory subsystem
+    * @group composite
+    */
   object MemorySubsystem extends Composite {
 
     /** Transporter modelling the MSMC controller
-      * @group transporter */
+      * @group transporter
+      */
     val msmc: SimpleTransporter = SimpleTransporter()
 
     /** Transporter modelling the DDR controller
-      * @group transporter */
+      * @group transporter
+      */
     val ddr_ctrl: SimpleTransporter = SimpleTransporter()
 
     /** Target modelling the SRAM peripheral
-      * @group transporter */
+      * @group transporter
+      */
     val sram: Target = Target()
 
     msmc link sram
     msmc link ddr_ctrl
   }
 
-  /** Composite representing Keystone ARM cores and their internal L1 cache 
-    * @group composite_def 
+  /** Composite representing Keystone ARM cores and their internal L1 cache
+    * @group composite_def
     */
   class ARMCore(armName: Symbol) extends Composite(armName) {
 
-    /**
-      * Enable to provide the name implicitly
-      * @param implicitName the name of the object/class inheriting from this class
-      *                     will be the name of composite
+    /** Enable to provide the name implicitly
+      * @param implicitName
+      *   the name of the object/class inheriting from this class will be the
+      *   name of composite
       */
     def this()(implicit implicitName: Name) = {
       this(implicitName.value)
     }
 
     /** Initiator modelling an ARM Core
-      * @group initiator */
+      * @group initiator
+      */
     val core: Initiator = Initiator()
 
     /** Transporter modelling the cache of the core
-      * @group target */
+      * @group target
+      */
     val cache: Target = Target()
 
     // ARM access to its private L1 cache
@@ -126,25 +137,25 @@ class MyProcPlatform(name: Symbol) extends Platform(name) {
   }
 
   /* -----------------------------------------------------------
-    * Global components
-    * ----------------------------------------------------------- */
+   * Global components
+   * ----------------------------------------------------------- */
 
-  /** Composite modelling ARM0 
-    * @group composite 
+  /** Composite modelling ARM0
+    * @group composite
     */
   val ARM0 = new ARMCore()
-  /**
-    * Composite modelling ARM1
-    * @group composite 
+
+  /** Composite modelling ARM1
+    * @group composite
     */
   val ARM1 = new ARMCore()
 
-  /** Initiator modelling ethernet peripheral 
+  /** Initiator modelling ethernet peripheral
     * @group initiator
     */
   val eth: Initiator = Initiator()
 
-  /** Transporter modelling AXI bus 
+  /** Transporter modelling AXI bus
     * @group transporter
     */
   val axi_bus: SimpleTransporter = SimpleTransporter()
@@ -153,21 +164,24 @@ class MyProcPlatform(name: Symbol) extends Platform(name) {
     * @group target
     */
   val spi: Target = Target()
-  /** Target modelling MPIC peripheral 
+
+  /** Target modelling MPIC peripheral
     * @group target
     */
   val mpic: Target = Target()
-  /** Target modelling DMA registers 
+
+  /** Target modelling DMA registers
     * @group target
     */
   val dma_reg: Target = Target()
-  /** Target modelling external DDR 
+
+  /** Target modelling external DDR
     * @group target
     */
   val ddr: Target = Target()
 
   /* -----------------------------------------------------------
-    * Physical connections
+   * Physical connections
       ----------------------------------------------------------- */
 
   // Each ARM core is connected to the internal interconnect
@@ -192,7 +206,7 @@ class MyProcPlatform(name: Symbol) extends Platform(name) {
   axi_bus link mpic
   axi_bus link MemorySubsystem.msmc
 
-  //MSMC connections
+  // MSMC connections
   MemorySubsystem.msmc link TeraNet.periph_bus
 
   MemorySubsystem.ddr_ctrl link ddr

diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcRoutingConfiguration.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcRoutingConfiguration.scala
@@ -1,31 +1,31 @@
-/*******************************************************************************
- * Copyright (c)  2023. ONERA
- * This file is part of PML Analyzer
- *
- * PML Analyzer is free software ;
- * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation ;
- * either version 2 of  the License, or (at your option) any later version.
- *
- * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License along with this program ;
- *  if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307  USA
- ******************************************************************************/
+/** *****************************************************************************
+  * Copyright (c) 2023. ONERA This file is part of PML Analyzer
+  *
+  * PML Analyzer is free software ; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published by the
+  * Free Software Foundation ; either version 2 of the License, or (at your
+  * option) any later version.
+  *
+  * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT
+  * ANY WARRANTY ; without even the implied warranty of MERCHANTABILITY or
+  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+  * for more details.
+  *
+  * You should have received a copy of the GNU Lesser General Public License
+  * along with this program ; if not, write to the Free Software Foundation,
+  * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+  */
 
 package onera.pmlanalyzer.pml.examples.mySys
 
 import onera.pmlanalyzer.pml.operators.*
 
-/**
-  * Routing constraints considered for simple Keystone
+/** Routing constraints considered for simple Keystone
   */
 trait MyProcRoutingConfiguration {
   self: MyProcPlatform =>
 
-  //Arm cores, ethernet and dma cannot use the periph_bus from msmc
+  // Arm cores, ethernet and dma cannot use the periph_bus from msmc
   ARM0.core cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus
   ARM1.core cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus
   eth cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus