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Syscall Boilerplate for riscvi32 (no interpreter implementation) #2751

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merged 1 commit into from
Nov 14, 2024

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@svv232 svv232 commented Nov 12, 2024

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…nding the iterator in the interpreter and adding to the column type
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codecov bot commented Nov 12, 2024

Codecov Report

Attention: Patch coverage is 0% with 20 lines in your changes missing coverage. Please review.

Project coverage is 72.07%. Comparing base (9c481e9) to head (d18fdd9).
Report is 13 commits behind head on master.

Files with missing lines Patch % Lines
o1vm/src/interpreters/riscv32i/column.rs 0.00% 10 Missing ⚠️
o1vm/src/interpreters/riscv32i/interpreter.rs 0.00% 10 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##           master    #2751      +/-   ##
==========================================
- Coverage   72.08%   72.07%   -0.01%     
==========================================
  Files         255      255              
  Lines       59090    59110      +20     
==========================================
+ Hits        42595    42604       +9     
- Misses      16495    16506      +11     

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@dannywillems dannywillems left a comment

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LGTM for the time being. Let's change it later.

Base automatically changed from dw/split-interpret-instruction-riscv32 to master November 14, 2024 14:45
@dannywillems dannywillems merged commit 5b6d530 into master Nov 14, 2024
7 of 8 checks passed
@dannywillems dannywillems deleted the sai/syscall-interpret-instruction-riscv32 branch November 14, 2024 14:46
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2 participants