Numato Lab AD9763 DAC Module

Numato Lab AD9763 DAC module tested using Numato Lab ElbertV2 FPGA board

Getting Started

install Xilinx ISE 14.7 webpack.
Download or clone this project and open using Xilinx ISE.
Code contains several modes(sine wave, triangle wave, etc.) which can be controlled using DIP switches of the FPGA board.
Code is simple and you can do necessary modifications.
Contraints are set to have the same values on both output channels.
Sysnthesize RTL and Program FPGA.
Enjoy..!

See also the list of contributors who participated in this project.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
_ngo		_ngo
_xmsgs		_xmsgs
iseconfig		iseconfig
xlnx_auto_0_xdb		xlnx_auto_0_xdb
xst/work		xst/work
.gitattributes		.gitattributes
ElbertDACverilog.gise		ElbertDACverilog.gise
ElbertDACverilog.xise		ElbertDACverilog.xise
Main.bld		Main.bld
Main.cmd_log		Main.cmd_log
Main.lso		Main.lso
Main.ncd		Main.ncd
Main.ngc		Main.ngc
Main.ngd		Main.ngd
Main.ngr		Main.ngr
Main.pad		Main.pad
Main.par		Main.par
Main.pcf		Main.pcf
Main.prj		Main.prj
Main.ptwx		Main.ptwx
Main.stx		Main.stx
Main.syr		Main.syr
Main.twr		Main.twr
Main.twx		Main.twx
Main.unroutes		Main.unroutes
Main.ut		Main.ut
Main.v		Main.v
Main.xpi		Main.xpi
Main.xst		Main.xst
Main_bitgen.xwbt		Main_bitgen.xwbt
Main_envsettings.html		Main_envsettings.html
Main_guide.ncd		Main_guide.ncd
Main_map.map		Main_map.map
Main_map.mrp		Main_map.mrp
Main_map.ncd		Main_map.ncd
Main_map.ngm		Main_map.ngm
Main_map.xrpt		Main_map.xrpt
Main_ngdbuild.xrpt		Main_ngdbuild.xrpt
Main_pad.csv		Main_pad.csv
Main_pad.txt		Main_pad.txt
Main_par.xrpt		Main_par.xrpt
Main_summary.html		Main_summary.html
Main_summary.xml		Main_summary.xml
Main_usage.xml		Main_usage.xml
Main_xst.xrpt		Main_xst.xrpt
README.md		README.md
constraints_file.ucf		constraints_file.ucf
main.bgn		main.bgn
main.bit		main.bit
main.drc		main.drc
usage_statistics_webtalk.html		usage_statistics_webtalk.html
webtalk.log		webtalk.log
webtalk_pn.xml		webtalk_pn.xml