Revert "attempt to fix init of _pipe0_read_addr"

This reverts commit fe3d445.
nRF24 · Oct 23, 2020 · 8df70db · 8df70db
1 parent fe3d445
commit 8df70db
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Showing 2 changed files with 8 additions and 6 deletions.
diff --git a/circuitpython_nrf24l01/rf24.py b/circuitpython_nrf24l01/rf24.py
@@ -84,7 +84,7 @@ def __init__(self, spi, csn, ce, spi_frequency=10000000):
             self._reg_write(0x50, 0x73)  # ensure they're enabled
         # init shadow copy of last RX_ADDR_P0 written to pipe 0 needed as
         # open_tx_pipe() appropriates pipe 0 for ACK packet
-        self._pipe0_read_addr = self._pipes[0]
+        self._pipe0_read_addr = None
         # init shadow copy of register about FIFO info
         self._fifo = 0
         # shadow copy of the TX_ADDRESS
@@ -238,9 +238,10 @@ def listen(self, is_rx):
         if self.listen != bool(is_rx):
             self.ce_pin.value = 0
             if is_rx:
-                for i, val in enumerate(self._pipe0_read_addr):
-                    self._pipes[0][i] = val
-                self._reg_write_bytes(RX_ADDR_P0, self._pipe0_read_addr)
+                if self._pipe0_read_addr is not None:
+                    for i, val in enumerate(self._pipe0_read_addr):
+                        self._pipes[0][i] = val
+                    self._reg_write_bytes(RX_ADDR_P0, self._pipe0_read_addr)
                 self._config = (self._config & 0xFC) | 3
                 self._reg_write(CONFIGURE, self._config)
                 time.sleep(0.00015)  # mandatory wait to power up radio

diff --git a/circuitpython_nrf24l01/rf24_lite.py b/circuitpython_nrf24l01/rf24_lite.py
@@ -23,7 +23,7 @@ def __init__(self, spi, csn, ce, spi_frequency=10000000):
         self._reg_write(1, 0x3F)
         self._reg_write(0x1D, 5)
         self._reg_write(4, 0x53)
-        self._pipe0_read_addr = self._reg_read_bytes(0x0A)
+        self._pipe0_read_addr = None
         self.channel = 76
         self.payload_length = 32
         self.flush_rx()
@@ -113,7 +113,8 @@ def listen(self, is_rx):
         if self.listen != bool(is_rx):
             self.ce_pin.value = 0
             if is_rx:
-                self._reg_write_bytes(0x0A, self._pipe0_read_addr)
+                if self._pipe0_read_addr is not None:
+                    self._reg_write_bytes(0x0A, self._pipe0_read_addr)
                 self._reg_write(0, (self._reg_read(0) & 0xFC) | 3)
                 time.sleep(0.00015)
                 self.flush_rx()