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contrib/ac97/trunk/rtl/verilog
contrib/ac97/trunk/rtl/verilog
 
 
ipcore_dir
ipcore_dir
 
 
LICENSE
LICENSE
 
 
README.md
README.md
 
 
audio_out_top_tb.vhd
audio_out_top_tb.vhd
 
 
audio_output_top.vhd
audio_output_top.vhd
 
 
envelope_generator.vhd
envelope_generator.vhd
 
 
fm2608.vhd
fm2608.vhd
 
 
fm_channel.vhd
fm_channel.vhd
 
 
fm_channel_tb.vhd
fm_channel_tb.vhd
 
 
minmax.vhd
minmax.vhd
 
 
mixer2.vhd
mixer2.vhd
 
 
operator.vhd
operator.vhd
 
 
operator_fb.vhd
operator_fb.vhd
 
 
operator_fb_tb.vhd
operator_fb_tb.vhd
 
 
operator_tb.vhd
operator_tb.vhd
 
 
phase_generator.vhd
phase_generator.vhd
 
 
phase_generator_tb.vhd
phase_generator_tb.vhd
 
 
pulse_generator.vhd
pulse_generator.vhd
 
 
register_playback.vhd
register_playback.vhd
 
 
signal_generator_sampled.vhd
signal_generator_sampled.vhd
 
 
signal_generator_square.vhd
signal_generator_square.vhd
 
 
sinetab.coe
sinetab.coe
 
 
timerb.vhd
timerb.vhd
 
 
timerb_tb.vhd
timerb_tb.vhd
 
 
xupv5_audio_out_top.ucf
xupv5_audio_out_top.ucf
 
 
xupv5_audio_out_top.vhd
xupv5_audio_out_top.vhd
 
 

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ym2608

VHDL clone of YM2608 (OPNA) sound chip

The source files here have been clean-room reverse engineered from the YM2608 C simulation described in fmgen, MAME, QEMU, and others. (Links and credits forthcoming.)

Thanks to Peter Barfuss (bofh) for helping understand this device and for general audio knowhow.

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VHDL clone of YM2608 (OPNA) sound chip

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