Image processing and extracting text from gray scale image (for fpga course project at university)
it is implemented and designed for virtex5-XC5VLX110T-FF1136
fpga board .
In image_to_coe.py
just pass image directory in to convert
function and run it .
One byte of data is stored for each image .
we implement a single port RAM using the Block Memory Generator ip core .
Images are loaded and read in readMemory.v
and connect to logic using intermediate.v
module .
logic.v
is a Verilog code receives the image from the input and separates the text from image and delivers it to the output in one clock ( combinational ).
logic output is connected to VGA_Controller.v
in topModule.v
.
VGA_Controller outputs used in .ucf
file .