Release build (v.2.2.0)

Ripes v2.2.0

New features

• Complete rework of the assembler/disassembler infrastructure:
  • Instructions taking immediate values now support simple expression evaluation. Furthermore, any label may be used as an immediate value.
  • New infrastructure significantly simplifies adding new ISAs and ISA extensions.
  • Added .equ directive, for defining constants in the assembler
• ISA extensions can now be toggled for a given processor. ISA extension changes are reflected in the assembler, syntax highlighter, and C compiler --march strings.
• A 6-stage dual-issue processor model is now available. This is the first processor model in Ripes capable of reaching an IPC > 1.
• A 5-stage with hazard detection but no forwarding is now available.
• Various toolbuttons have been moved to clean up the UI.
• Various performance improvements to remove unnecessary model and UI updates.
• Modified cache simulator:
  • The cache simulator now has a dedicated tab.
  • The cache view now visualizes how the block and line indices map into the cache.
  • It is possible to save and load user cache presets
  • More focus on cache statistics, which includes real-time plotting of cache variable ratios as well as plotting of the moving average of a given ratio.
• A new tab has been added, the 'memory' tab. Here, the scrollable memory viewer is placed, alongside a new view of the memory map of the processor (segments of the loaded program and I/O devices).
• Support for memory mapped I/O is now available. Please refer to the wiki page on memory-mapped I/O for more information.

Bug fixes:

• Fixes issue with compiler paths containing " " (space) characters not being recognized as valid.
• System call function register is now explicitly stated when showing system call error messages, as well as in the system call help menu.
• The new assembler infrastructure fixes quite a few bugs in the old assembler.

VSRTL:

• Added support for darkmode-style circuit drawing
• Removed an unneeded dynamic_cast which resulted in a large speedup, due to the elimination of a vtable lookup for each port in the design, for each cycle.
• Remove use of templated value<T> function in favor of uValue/sValue which is bitwidth aware.