Added a new example with NIOSV-g type Soft-CPU booting from EPCS, but…

… executing from Tightly Coupled Memory (TCMEM) for PROG and DATA.

7.niosv_soc_epcs_sdram_iic_freertos/quartus/db/niosv_soc_epcs_sdram_iic_freertos_top.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Standard Edition
 Version_Index = 570679552
-Creation_Time = Tue Oct  1 21:20:52 2024
+Creation_Time = Sun Oct 13 02:12:38 2024

7.niosv_soc_epcs_sdram_iic_freertos/quartus/db/niosv_soc_epcs_sdram_iic_freertos_top.tmw_info

@@ -1,7 +1,4 @@
-start_full_compilation:s:00:01:47
-start_analysis_synthesis:s:00:00:49-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:45-start_full_compilation
-start_assembler:s:00:00:04-start_full_compilation
-start_timing_analyzer:s:00:00:05-start_full_compilation
-start_eda_netlist_writer:s:00:00:04-start_full_compilation
+start_full_compilation:s
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation

7.niosv_soc_epcs_sdram_iic_freertos/quartus/niosv_soc_epcs_sdram_iic_freertos_top.qsf

@@ -207,4 +207,5 @@ set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

8.niosv_g_soc_epcs_tcmem_iic/constraints/pinning_de0nano_brd.tcl

@@ -0,0 +1,49 @@
+# Using Terasic's DE0 NANO (Intel EP4CE22F17C6F FPGA) Evaluation Board Kit 
+# Set (allocate) the pins to the appropriate ports of the entity/module 
+
+# The main clock source for the FPGA - external
+set_location_assignment PIN_R8 -to EXT_CLK_50M ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_CLK_50M ; 
+
+# Push buttons - active low (GND) - inputs 
+set_location_assignment PIN_J15 -to BTN_RESET_n ; # KEY0 , will be used to cause a general reset 
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_RESET_n ;
+set_location_assignment PIN_E1 -to BTN_USER_n ; # KEY1 , will be used for user interaction (of some sort)
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_USER_n ;
+
+# Toggle switches - SW[x] - inputs 
+set_location_assignment PIN_M1 -to DIPSW[0] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIPSW[0] ;
+set_location_assignment PIN_T8 -to DIPSW[1] ; 
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIPSW[1] ;
+set_location_assignment PIN_B9 -to DIPSW[2] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIPSW[2] ;
+set_location_assignment PIN_M15 -to DIPSW[3] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIPSW[3] ;
+
+# LEDs Green - LEDG[x] - outputs 
+set_location_assignment PIN_A15 -to LEDG[0] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0] ;
+set_location_assignment PIN_A13 -to LEDG[1] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1] ;
+set_location_assignment PIN_B13 -to LEDG[2] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2] ;
+set_location_assignment PIN_A11 -to LEDG[3] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3] ;
+set_location_assignment PIN_D1 -to LEDG[4] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4] ;
+set_location_assignment PIN_F3 -to LEDG[5] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5] ;
+set_location_assignment PIN_B1 -to LEDG[6] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6] ;
+set_location_assignment PIN_L3 -to LEDG[7] ;
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7] ;
+
+# UART communication - RX and TX (8N1 - 115200 baud/s) 
+set_location_assignment PIN_C9 -to UART_RXD ; # GPIO-0 connector (header) - GPIO_024 (pin 31)
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD ;
+set_location_assignment PIN_D9 -to UART_TXD ; # GPIO-0 connector (header) - GPIO_025 (pin 32)
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD ;
+
+# Set the rest of the unused pins to inputs (in tri-state) 
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

8.niosv_g_soc_epcs_tcmem_iic/constraints/timing_de0nano_brd.sdc

@@ -0,0 +1,12 @@
+# Using Terasic's DE0 NANO (Intel EP4CE22F17C6F FPGA) Evaluation Board Kit 
+# setting
+set_time_format -unit ns -decimal_places 3
+
+# clocks - this is the main external clock of DE0-NANO of the FPGA - at 50 [MHz]
+create_clock -name EXT_CLK_50M -period 20.000 [get_ports {EXT_CLK_50M}]
+
+# define all PLL clocks 
+derive_pll_clocks 
+
+# compute the jitter behavior of the PLLs 
+derive_clock_uncertainty 

8.niosv_g_soc_epcs_tcmem_iic/hdl/niosv_g_soc_epcs_tcmem_iic_top.sv

@@ -0,0 +1,74 @@
+// Board: Terasic DE0-NANO (Cyclone IV E)
+// File     : niosv_g_soc_epcs_tcmem_iic_top.sv
+//-----------------------------------------------------------------------------
+// Language : SystemVerilog
+//-----------------------------------------------------------------------------
+// Description:
+//   Top level of project - NO/SMALL AMOUNT LOGIC ALLOWED AT THIS LEVEL
+//-----------------------------------------------------------------------------
+
+// Top Level - Parameters & External Pins
+module niosv_g_soc_epcs_tcmem_iic_top 
+#(
+  parameter EXT_CLOCK_FREQ = 50000000, // in [Hz]
+  parameter EXT_CLOCK_PERIOD = 20.000, // in [ns]
+  parameter INT_PLL_CLOCK_FREQ = 100000000, // in [Hz]
+  parameter INT_PLL_CLOCK_PERIOD = 10.000   // in [ns]
+)(
+  // Clocks:
+  input         EXT_CLK_50M,      // Main external clock of the DE0-NANO (FPGA) board - 50 [MHz] 
+  // Buttons: 
+  input         BTN_RESET_n,        // push-button for main Fabric/SoC (general) reset - active-low
+  input         BTN_USER_n,         // push button for user level interaction - active-low
+  // DIP Switches:
+  input    [3:0] DIPSW, 
+  // LEDs (green) :
+  output   [7:0] LEDG,
+  // UART Communication: 
+  input UART_RXD,
+  output UART_TXD
+);
+
+  wire  pll_areset  ;  // This is an (output) signal we must set/clear and provide it to the NIOSV_SOC system  
+  wire  pll_locked  ;  // This is an (input) signal we must read from the NIOSV_SOC system, to infer if the pll clock is locked.
+  reg   [7:0] pwrup_timer ; // For the POR reset - a timer counter (unsigned) that is going to allow some time to pass. 
+  // POR (reset) generator with hold-up 
+  always_ff@(posedge EXT_CLK_50M or negedge BTN_RESET_n)
+    begin
+	if(~BTN_RESET_n) // Asyncrhonous reset 
+	  begin
+	  pll_areset <= 1'b1;  // assert (active-high) the pll reset
+	  pwrup_timer <= 7'h0; // zero the timer
+	  end 
+	else // Syncrhonous process
+      begin 	  
+	  if(pwrup_timer != 8'd127) // Check if enought the power up time had elapsed
+        begin
+	    pll_areset  <= 1'b1; //  keep asserted (active-high) the internal reset
+	    pwrup_timer++ ; // increment the timer
+	    end 
+      else // If enough time had passed ...
+	    begin
+		pll_areset <= 1'b0 ; // release (deassert) the pll from reset
+		end
+	  end
+    end 		
+
+//-----------------------------------------------------------------------------
+// MODULE INSTANTIATIONS
+//-----------------------------------------------------------------------------
+
+// NIOS-V 'G' type overall SoC - Qsys
+NIOSV_G_SOC NIOSV_G_SOC_inst (
+	.reset_bridge_in_reset_n_reset_n   (BTN_RESET_n),  //    reset_bridge_in_reset_n.reset_n
+	.clock_bridge_in_clk_clk           (EXT_CLK_50M),  //        clock_bridge_in_clk.clk
+	.altpll_clks_areset_conduit_export (pll_areset),   // altpll_clks_areset_conduit.export
+	.altpll_clks_locked_conduit_export (pll_locked),   // altpll_clks_locked_conduit.export
+	.serial_uart_com_externals_rxd     (UART_RXD),     //  serial_uart_com_externals.rxd
+	.serial_uart_com_externals_txd     (UART_TXD),     //                           .txd
+	.gpi0_btn_externals_export         (BTN_USER_n),   //         gpi0_btn_externals.export
+	.gpi1_dipsw_externals_export       (DIPSW),        //       gpi1_dipsw_externals.export
+	.gpo2_ledg_externals_export        (LEDG)          //        gpo2_ledg_externals.export
+);
+
+endmodule

8.niosv_g_soc_epcs_tcmem_iic/hdl/niosv_g_soc_epcs_tcmem_iic_top.sv.bak

@@ -0,0 +1,95 @@
+// Board: Terasic DE0-NANO (Cyclone IV E)
+// File     : niosv_g_soc_epcs_tcmem_iic_top.sv
+//-----------------------------------------------------------------------------
+// Language : SystemVerilog
+//-----------------------------------------------------------------------------
+// Description:
+//   Top level of project - NO/SMALL AMOUNT LOGIC ALLOWED AT THIS LEVEL
+//-----------------------------------------------------------------------------
+
+// Top Level - Parameters & External Pins
+module niosv_g_soc_epcs_tcmem_iic_top 
+#(
+  parameter EXT_CLOCK_FREQ = 50000000, // in [Hz]
+  parameter EXT_CLOCK_PERIOD = 20.000, // in [ns]
+  parameter INT_PLL_CLOCK_FREQ = 100000000, // in [Hz]
+  parameter INT_PLL_CLOCK_PERIOD = 10.000   // in [ns]
+)(
+  // Clocks:
+  input         EXT_CLK_50M,      // Main external clock of the DE0-NANO (FPGA) board - 50 [MHz] 
+  // SDRAM (external chip 32MB (16Mbit x 16) : 
+  output [12:0]	SDRAM_ADDR,
+  output  [1:0]	SDRAM_BA,
+  output       	SDRAM_CAS_n,
+  output       	SDRAM_CKE,
+  output       	SDRAM_CLK, 
+  output       	SDRAM_CS_n,
+  inout  [15:0]	SDRAM_DQ,
+  output  [1:0]	SDRAM_DQM,
+  output       	SDRAM_RAS_n,
+  output       	SDRAM_WE_n,
+  // Buttons: 
+  input         BTN_RESET_n,        // push-button for main Fabric/SoC (general) reset - active-low
+  input         BTN_USER_n,         // push button for user level interaction - active-low
+  // DIP Switches:
+  input    [3:0] DIPSW, 
+  // LEDs (green) :
+  output   [7:0] LEDG,
+  // UART Communication: 
+  input UART_RXD,
+  output UART_TXD
+);
+
+  wire  pll_areset  ;  // This is an (output) signal we must set/clear and provide it to the NIOSV_SOC system  
+  wire  pll_locked  ;  // This is an (input) signal we must read from the NIOSV_SOC system, to infer if the pll clock is locked.
+  reg   [7:0] pwrup_timer ; // For the POR reset - a timer counter (unsigned) that is going to allow some time to pass. 
+  // POR (reset) generator with hold-up 
+  always_ff@(posedge EXT_CLK_50M or negedge BTN_RESET_n)
+    begin
+	if(~BTN_RESET_n) // Asyncrhonous reset 
+	  begin
+	  pll_areset <= 1'b1;  // assert (active-high) the pll reset
+	  pwrup_timer <= 7'h0; // zero the timer
+	  end 
+	else // Syncrhonous process
+      begin 	  
+	  if(pwrup_timer != 8'd127) // Check if enought the power up time had elapsed
+        begin
+	    pll_areset  <= 1'b1; //  keep asserted (active-high) the internal reset
+	    pwrup_timer++ ; // increment the timer
+	    end 
+      else // If enough time had passed ...
+	    begin
+		pll_areset <= 1'b0 ; // release (deassert) the pll from reset
+		end
+	  end
+    end 		
+
+//-----------------------------------------------------------------------------
+// MODULE INSTANTIATIONS
+//-----------------------------------------------------------------------------
+
+// NIOS-V 'G' type overall SoC - Qsys
+NIOSV_G_SOC NIOSV_G_SOC_inst (
+	.reset_bridge_in_reset_n_reset_n   (BTN_RESET_n),  //    reset_bridge_in_reset_n.reset_n
+	.clock_bridge_in_clk_clk           (EXT_CLK_50M),  //        clock_bridge_in_clk.clk
+	.altpll_clks_areset_conduit_export (pll_areset),   // altpll_clks_areset_conduit.export
+	.altpll_clks_locked_conduit_export (pll_locked),   // altpll_clks_locked_conduit.export
+	.altpll_clks_c1_phaseshift_clk     (SDRAM_CLK),    //  altpll_clks_c1_phaseshift.clk
+	.sdram_controller_externals_addr   (SDRAM_ADDR),   // sdram_controller_externals.addr
+	.sdram_controller_externals_ba     (SDRAM_BA),     //                           .ba
+	.sdram_controller_externals_cas_n  (SDRAM_CAS_n),  //                           .cas_n
+	.sdram_controller_externals_cke    (SDRAM_CKE),    //                           .cke
+	.sdram_controller_externals_cs_n   (SDRAM_CS_n),   //                           .cs_n
+	.sdram_controller_externals_dq     (SDRAM_DQ),     //                           .dq
+	.sdram_controller_externals_dqm    (SDRAM_DQM),    //                           .dqm
+	.sdram_controller_externals_ras_n  (SDRAM_RAS_n),  //                           .ras_n
+	.sdram_controller_externals_we_n   (SDRAM_WE_n),   //                           .we_n
+	.serial_uart_com_externals_rxd     (UART_RXD),     //  serial_uart_com_externals.rxd
+	.serial_uart_com_externals_txd     (UART_TXD),     //                           .txd
+	.gpi0_btn_externals_export         (BTN_USER_n),   //         gpi0_btn_externals.export
+	.gpi1_dipsw_externals_export       (DIPSW),        //       gpi1_dipsw_externals.export
+	.gpo2_ledg_externals_export        (LEDG)          //        gpo2_ledg_externals.export
+);
+
+endmodule

8.niosv_g_soc_epcs_tcmem_iic/qsys/.qsys_edit/filters.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="23.1" />

8.niosv_g_soc_epcs_tcmem_iic/qsys/.qsys_edit/preferences.xml

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="143" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Library,Project" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>