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IP_Catalog

Copyright (c) 2022-2024 Rapid Silicon Inc.

This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.

Contact [email protected] for non-GPL Commercial Licensing option.

IP Catalog is an IP library for Raptor toolchain.

IP_Catalog
	rapidsilicon
		ip/
		├── ahb2axi_bridge
		├── ahb_sram
		├── axi2ahb_bridge
		├── axi2axilite_bridge
		├── axi_async_fifo
		├── axi_cdma
		├── axi_crossbar
		├── axi_dma
		├── axi_dpram
		├── axi_fifo
		├── axi_interconnect
		├── axil_crossbar
		├── axil_eio
		├── axil_gpio
		├── axil_interconnect
		├── axil_quadspi
		├── axil_tmp_sensor
		├── axil_uart16550
		├── axi_ram
		├── axi_register
		├── axis_adapter
		├── axis_async_fifo
		├── axis_broadcast
		├── axi_sdram
		├── axis_fifo
		├── axis_interconnect
		├── axis_pipeline_register
		├── axis_ram_switch
		├── axis_switch
		├── axis_uart
		├── boot_clock
		├── ddr_sdram
		├── dsp_generator
		├── ethernet_mac
		├── fifo_generator
		├── fir_generator
		├── i2c_master
		├── i2c_slave
		├── io_configurator
		├── jtag_to_axi
		├── ocla
		├── on_chip_memory
		├── pll
		├── priority_encoder
		├── reset_release
		└── vexriscv_cpu

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IP Catalog for Raptor.

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  • Verilog 56.2%
  • Python 34.2%
  • SystemVerilog 5.9%
  • C++ 1.7%
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