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Register map generator for VHDL digital designs and Embedded Systems.

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IP-XACT Register map generation tool

Generator of register map design sources and documentation from IP-XACT format.

Following artifact are generated: - Lyx documentation - VHDL package with constants definition for testbench or design - C Header File - Synthesizable VHDL RTL implementation of register map.

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Register map generator for VHDL digital designs and Embedded Systems.

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  • Python 79.1%
  • VHDL 20.9%